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| author | Simon Pilgrim <llvm-dev@redking.me.uk> | 2019-02-25 11:19:37 +0000 |
|---|---|---|
| committer | Simon Pilgrim <llvm-dev@redking.me.uk> | 2019-02-25 11:19:37 +0000 |
| commit | c61f1e8e6cda9afad8b2b4cd6e95f814ca82685c (patch) | |
| tree | 77c28f237f5e609739483bab6ad0cedf30153ccc /llvm/test/CodeGen/X86/combine-adc.ll | |
| parent | fd99780c0941c7576bb271d7e58e6553afe9db00 (diff) | |
| download | bcm5719-llvm-c61f1e8e6cda9afad8b2b4cd6e95f814ca82685c.tar.gz bcm5719-llvm-c61f1e8e6cda9afad8b2b4cd6e95f814ca82685c.zip | |
[X86] Merge ISD::ADD/SUB nodes into X86ISD::ADD/SUB equivalents (PR40483)
Avoid ADD/SUB instruction duplication by reusing the X86ISD::ADD/SUB results.
Includes ADD commutation - I tried to include NEG+SUB SUB commutation as well but this causes regressions as we don't have good combine coverage to simplify X86ISD::SUB.
Differential Revision: https://reviews.llvm.org/D58597
llvm-svn: 354771
Diffstat (limited to 'llvm/test/CodeGen/X86/combine-adc.ll')
| -rw-r--r-- | llvm/test/CodeGen/X86/combine-adc.ll | 52 |
1 files changed, 15 insertions, 37 deletions
diff --git a/llvm/test/CodeGen/X86/combine-adc.ll b/llvm/test/CodeGen/X86/combine-adc.ll index 0f11f3159f8..63021942fde 100644 --- a/llvm/test/CodeGen/X86/combine-adc.ll +++ b/llvm/test/CodeGen/X86/combine-adc.ll @@ -5,33 +5,22 @@ define i32 @PR40483_add1(i32*, i32) nounwind { ; X86-LABEL: PR40483_add1: ; X86: # %bb.0: -; X86-NEXT: pushl %esi ; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx -; X86-NEXT: movl {{[0-9]+}}(%esp), %edx -; X86-NEXT: movl (%edx), %esi -; X86-NEXT: leal (%esi,%ecx), %eax -; X86-NEXT: addl %ecx, %esi -; X86-NEXT: movl %esi, (%edx) -; X86-NEXT: jae .LBB0_1 -; X86-NEXT: # %bb.2: +; X86-NEXT: movl (%ecx), %eax +; X86-NEXT: addl {{[0-9]+}}(%esp), %eax +; X86-NEXT: movl %eax, (%ecx) +; X86-NEXT: jae .LBB0_2 +; X86-NEXT: # %bb.1: ; X86-NEXT: xorl %eax, %eax -; X86-NEXT: popl %esi -; X86-NEXT: retl -; X86-NEXT: .LBB0_1: -; X86-NEXT: orl %eax, %eax -; X86-NEXT: popl %esi +; X86-NEXT: .LBB0_2: ; X86-NEXT: retl ; ; X64-LABEL: PR40483_add1: ; X64: # %bb.0: -; X64-NEXT: # kill: def $esi killed $esi def $rsi -; X64-NEXT: movl (%rdi), %ecx -; X64-NEXT: leal (%rcx,%rsi), %edx -; X64-NEXT: orl %edx, %edx ; X64-NEXT: xorl %eax, %eax -; X64-NEXT: addl %esi, %ecx -; X64-NEXT: movl %ecx, (%rdi) -; X64-NEXT: cmovael %edx, %eax +; X64-NEXT: addl (%rdi), %esi +; X64-NEXT: movl %esi, (%rdi) +; X64-NEXT: cmovael %esi, %eax ; X64-NEXT: retq %3 = load i32, i32* %0, align 8 %4 = tail call { i8, i32 } @llvm.x86.addcarry.32(i8 0, i32 %3, i32 %1) @@ -48,34 +37,23 @@ define i32 @PR40483_add1(i32*, i32) nounwind { define i32 @PR40483_add2(i32*, i32) nounwind { ; X86-LABEL: PR40483_add2: ; X86: # %bb.0: -; X86-NEXT: pushl %edi -; X86-NEXT: pushl %esi ; X86-NEXT: movl {{[0-9]+}}(%esp), %edx -; X86-NEXT: movl {{[0-9]+}}(%esp), %esi -; X86-NEXT: movl (%esi), %edi -; X86-NEXT: leal (%edi,%edx), %ecx +; X86-NEXT: movl (%edx), %ecx ; X86-NEXT: xorl %eax, %eax -; X86-NEXT: addl %edx, %edi -; X86-NEXT: movl %edi, (%esi) +; X86-NEXT: addl {{[0-9]+}}(%esp), %ecx +; X86-NEXT: movl %ecx, (%edx) ; X86-NEXT: jae .LBB1_2 ; X86-NEXT: # %bb.1: -; X86-NEXT: orl %ecx, %ecx ; X86-NEXT: movl %ecx, %eax ; X86-NEXT: .LBB1_2: -; X86-NEXT: popl %esi -; X86-NEXT: popl %edi ; X86-NEXT: retl ; ; X64-LABEL: PR40483_add2: ; X64: # %bb.0: -; X64-NEXT: # kill: def $esi killed $esi def $rsi -; X64-NEXT: movl (%rdi), %ecx -; X64-NEXT: leal (%rcx,%rsi), %edx -; X64-NEXT: orl %edx, %edx ; X64-NEXT: xorl %eax, %eax -; X64-NEXT: addl %esi, %ecx -; X64-NEXT: movl %ecx, (%rdi) -; X64-NEXT: cmovbl %edx, %eax +; X64-NEXT: addl (%rdi), %esi +; X64-NEXT: movl %esi, (%rdi) +; X64-NEXT: cmovbl %esi, %eax ; X64-NEXT: retq %3 = load i32, i32* %0, align 8 %4 = tail call { i8, i32 } @llvm.x86.addcarry.32(i8 0, i32 %3, i32 %1) |
