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| author | Craig Topper <craig.topper@intel.com> | 2017-08-30 05:00:35 +0000 |
|---|---|---|
| committer | Craig Topper <craig.topper@intel.com> | 2017-08-30 05:00:35 +0000 |
| commit | ef1f71669eb9b626d0dfc74aa11ffba05e5fb1e5 (patch) | |
| tree | ff24ad9d4900b9faf9fe5f9088fb64b775d44b7c /llvm/test/CodeGen/WebAssembly/non-executable-stack.ll | |
| parent | e3bbb68b0c5a79afb74072eaab79d2d3262f0e28 (diff) | |
| download | bcm5719-llvm-ef1f71669eb9b626d0dfc74aa11ffba05e5fb1e5.tar.gz bcm5719-llvm-ef1f71669eb9b626d0dfc74aa11ffba05e5fb1e5.zip | |
[X86] Apply SlowIncDec feature to Sandybridge/Ivybridge CPUs as well
Currently we start applying this on Haswell and newer. I don't believe anything changed in the Haswell architecture to make this the right cutoff point. The partial flag handling around this has been roughly the same since Sandybridge.
Differential Revision: https://reviews.llvm.org/D37250
llvm-svn: 312099
Diffstat (limited to 'llvm/test/CodeGen/WebAssembly/non-executable-stack.ll')
0 files changed, 0 insertions, 0 deletions
