[ARM] Add some missing thumb1 opcodes to enable peephole optimisation of CMPs

This adds a number of missing Thumb1 opcodes so that the peephole optimiser can
remove redundant CMP instructions.

Reapplying this after the first attempt broke non-thumb1 code as the t2ADDri
instruction can be used with frame indices. In thumb1 we use tADDframe.

Differential Revision: https://reviews.llvm.org/D57833

llvm-svn: 354667

1 files changed, 226 insertions, 0 deletions

diff --git a/llvm/test/CodeGen/Thumb/peephole-cmp.mir b/llvm/test/CodeGen/Thumb/peephole-cmp.mir
new file mode 100644
index 00000000000..33b1581cdce
--- /dev/null
+++ b/llvm/test/CodeGen/Thumb/peephole-cmp.mir
@@ -0,0 +1,226 @@
+# RUN: llc -mtriple thumbv8m.base-none-eabi -run-pass=peephole-opt -verify-machineinstrs -o - %s | FileCheck %s
+--- |
+  target datalayout = "e-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64"
+  target triple = "thumbv8m.base-none-none-eabi"
+
+  define i32 @test_subrr(i32 %a, i32 %b) { ret i32 %a }
+  define i32 @test_subrr_c(i32 %a, i32 %b) { ret i32 %a }
+  define i32 @test_subri3(i32 %a) { ret i32 %a }
+  define i32 @test_subri8(i32 %a) { ret i32 %a }
+  define i32 @test_addrr(i32 %a) { ret i32 %a }
+  define i32 @test_addri3(i32 %a) { ret i32 %a }
+  define i32 @test_addri8(i32 %a) { ret i32 %a }
+
+...
+---
+name:            test_subrr
+liveins:
+  - { reg: '$r0', virtual-reg: '%1' }
+  - { reg: '$r1', virtual-reg: '%2' }
+body:             |
+  bb.0:
+    successors: %bb.2(0x40000000), %bb.1(0x40000000)
+    liveins: $r0, $r1
+
+    %2:tgpr = COPY $r1
+    %1:tgpr = COPY $r0
+    %0:tgpr, $cpsr = tSUBrr %2, %1, 14, $noreg
+    tCMPr %1, %2, 14, $noreg, implicit-def $cpsr
+    tBcc %bb.2, 3, $cpsr
+    tB %bb.1, 14, $noreg
+
+  bb.1:
+    $r0 = COPY %0
+    tBX_RET 14, $noreg, implicit $r0
+
+  bb.2:
+    %3:tgpr, dead $cpsr = tMOVi8 0, 14, $noreg
+    $r0 = COPY %3
+    tBX_RET 14, $noreg, implicit $r0
+
+# CHECK-LABEL: name: test_subrr
+# CHECK:      [[COPY1:%[0-9]+]]:tgpr = COPY $r1
+# CHECK-NEXT: [[COPY0:%[0-9]+]]:tgpr = COPY $r0
+# CHECK-NEXT: [[ADD:%[0-9]+]]:tgpr, $cpsr = tSUBrr [[COPY1]], [[COPY0]], 14, $noreg
+# CHECK-NEXT: tBcc %bb.2, 8, $cpsr
+...
+---
+name:            test_subrr_c
+liveins:
+  - { reg: '$r0', virtual-reg: '%1' }
+  - { reg: '$r1', virtual-reg: '%2' }
+body:             |
+  bb.0:
+    successors: %bb.2(0x40000000), %bb.1(0x40000000)
+    liveins: $r0, $r1
+
+    %2:tgpr = COPY $r1
+    %1:tgpr = COPY $r0
+    %0:tgpr, $cpsr = tSUBrr %1, %2, 14, $noreg
+    tCMPr %1, %2, 14, $noreg, implicit-def $cpsr
+    tBcc %bb.2, 3, $cpsr
+    tB %bb.1, 14, $noreg
+
+  bb.1:
+    $r0 = COPY %0
+    tBX_RET 14, $noreg, implicit $r0
+
+  bb.2:
+    %3:tgpr, dead $cpsr = tMOVi8 0, 14, $noreg
+    $r0 = COPY %3
+    tBX_RET 14, $noreg, implicit $r0
+
+# CHECK-LABEL: name: test_subrr_c
+# CHECK:      [[COPY1:%[0-9]+]]:tgpr = COPY $r1
+# CHECK-NEXT: [[COPY0:%[0-9]+]]:tgpr = COPY $r0
+# CHECK-NEXT: [[ADD:%[0-9]+]]:tgpr, $cpsr = tSUBrr [[COPY0]], [[COPY1]], 14, $noreg
+# CHECK-NEXT: tBcc %bb.2, 3, $cpsr
+...
+---
+name:            test_subri3
+liveins:
+  - { reg: '$r0', virtual-reg: '%1' }
+body:             |
+  bb.0:
+    successors: %bb.2(0x40000000), %bb.1(0x40000000)
+    liveins: $r0
+
+    %1:tgpr = COPY $r0
+    %0:tgpr, $cpsr = tSUBi3 %1, 1, 14, $noreg
+    tCMPi8 %1, 1, 14, $noreg, implicit-def $cpsr
+    tBcc %bb.2, 3, $cpsr
+    tB %bb.1, 14, $noreg
+
+  bb.1:
+    $r0 = COPY %0
+    tBX_RET 14, $noreg, implicit $r0
+
+  bb.2:
+    %2:tgpr, dead $cpsr = tMOVi8 0, 14, $noreg
+    $r0 = COPY %2
+    tBX_RET 14, $noreg, implicit $r0
+
+# CHECK-LABEL: name: test_subri3
+# CHECK:      [[COPY:%[0-9]+]]:tgpr = COPY $r0
+# CHECK-NEXT: [[ADD:%[0-9]+]]:tgpr, $cpsr = tSUBi3 [[COPY]], 1, 14, $noreg
+# CHECK-NEXT: tBcc %bb.2, 3, $cpsr
+...
+---
+name:            test_subri8
+liveins:
+  - { reg: '$r0', virtual-reg: '%1' }
+body:             |
+  bb.0:
+    successors: %bb.2(0x40000000), %bb.1(0x40000000)
+    liveins: $r0
+
+    %1:tgpr = COPY $r0
+    %0:tgpr, $cpsr = tSUBi8 %1, 1, 14, $noreg
+    tCMPi8 %1, 1, 14, $noreg, implicit-def $cpsr
+    tBcc %bb.2, 3, $cpsr
+    tB %bb.1, 14, $noreg
+
+  bb.1:
+    $r0 = COPY %0
+    tBX_RET 14, $noreg, implicit $r0
+
+  bb.2:
+    %2:tgpr, dead $cpsr = tMOVi8 0, 14, $noreg
+    $r0 = COPY %2
+    tBX_RET 14, $noreg, implicit $r0
+
+# CHECK-LABEL: name: test_subri8
+# CHECK:      [[COPY:%[0-9]+]]:tgpr = COPY $r0
+# CHECK-NEXT: [[ADD:%[0-9]+]]:tgpr, $cpsr = tSUBi8 [[COPY]], 1, 14, $noreg
+# CHECK-NEXT: tBcc %bb.2, 3, $cpsr
+...
+---
+name:            test_addrr
+liveins:
+  - { reg: '$r0', virtual-reg: '%1' }
+  - { reg: '$r1', virtual-reg: '%2' }
+body:             |
+  bb.0:
+    successors: %bb.2(0x40000000), %bb.1(0x40000000)
+    liveins: $r0, $r1
+
+    %2:tgpr = COPY $r1
+    %1:tgpr = COPY $r0
+    %0:tgpr, $cpsr = tADDrr %2, %1, 14, $noreg
+    tCMPr %0, %2, 14, $noreg, implicit-def $cpsr
+    tBcc %bb.2, 3, $cpsr
+    tB %bb.1, 14, $noreg
+
+  bb.1:
+    $r0 = COPY %0
+    tBX_RET 14, $noreg, implicit $r0
+
+  bb.2:
+    %3:tgpr, dead $cpsr = tMOVi8 0, 14, $noreg
+    $r0 = COPY %3
+    tBX_RET 14, $noreg, implicit $r0
+
+# CHECK-LABEL: name: test_addrr
+# CHECK:      [[COPY1:%[0-9]+]]:tgpr = COPY $r1
+# CHECK-NEXT: [[COPY0:%[0-9]+]]:tgpr = COPY $r0
+# CHECK-NEXT: [[ADD:%[0-9]+]]:tgpr, $cpsr = tADDrr [[COPY1]], [[COPY0]], 14, $noreg
+# CHECK-NEXT: tBcc %bb.2, 2, $cpsr
+...
+---
+name:            test_addri3
+liveins:
+  - { reg: '$r0', virtual-reg: '%1' }
+body:             |
+  bb.0:
+    successors: %bb.2(0x40000000), %bb.1(0x40000000)
+    liveins: $r0
+
+    %0:tgpr = COPY $r0
+    %1:tgpr, $cpsr = tADDi3 %0, 1, 14, $noreg
+    tCMPr %1, %0, 14, $noreg, implicit-def $cpsr
+    tBcc %bb.2, 3, $cpsr
+    tB %bb.1, 14, $noreg
+
+  bb.1:
+    $r0 = COPY %0
+    tBX_RET 14, $noreg, implicit $r0
+
+  bb.2:
+    %2:tgpr, dead $cpsr = tMOVi8 0, 14, $noreg
+    $r0 = COPY %2
+    tBX_RET 14, $noreg, implicit $r0
+
+# CHECK-LABEL: name: test_addri3
+# CHECK:      [[COPY:%[0-9]+]]:tgpr = COPY $r0
+# CHECK-NEXT: [[ADD:%[0-9]+]]:tgpr, $cpsr = tADDi3 [[COPY]], 1, 14, $noreg
+# CHECK-NEXT: tBcc %bb.2, 2, $cpsr
+...
+---
+name:            test_addri8
+liveins:
+  - { reg: '$r0', virtual-reg: '%1' }
+body:             |
+  bb.0:
+    successors: %bb.2(0x40000000), %bb.1(0x40000000)
+    liveins: $r0
+
+    %0:tgpr = COPY $r0
+    %1:tgpr, $cpsr = tADDi8 %0, 10, 14, $noreg
+    tCMPr %1, %0, 14, $noreg, implicit-def $cpsr
+    tBcc %bb.2, 3, $cpsr
+    tB %bb.1, 14, $noreg
+
+  bb.1:
+    $r0 = COPY %0
+    tBX_RET 14, $noreg, implicit $r0
+
+  bb.2:
+    %2:tgpr, dead $cpsr = tMOVi8 0, 14, $noreg
+    $r0 = COPY %2
+    tBX_RET 14, $noreg, implicit $r0
+
+# CHECK-LABEL: name: test_addri8
+# CHECK:      [[COPY:%[0-9]+]]:tgpr = COPY $r0
+# CHECK-NEXT: [[ADD:%[0-9]+]]:tgpr, $cpsr = tADDi8 [[COPY]], 10, 14, $noreg
+# CHECK-NEXT: tBcc %bb.2, 2, $cpsr
+...