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| author | Matthias Braun <matze@braunis.de> | 2017-09-28 23:12:06 +0000 |
|---|---|---|
| committer | Matthias Braun <matze@braunis.de> | 2017-09-28 23:12:06 +0000 |
| commit | 51687912a4da910426c8daf40994fde3a9ac3520 (patch) | |
| tree | 6fc94a09eb23f18e965e47e6b164f0f6606cb4fe /llvm/test/CodeGen/Thumb | |
| parent | 195b25cf3cbde92e8613465571b5f3511c5cc69d (diff) | |
| download | bcm5719-llvm-51687912a4da910426c8daf40994fde3a9ac3520.tar.gz bcm5719-llvm-51687912a4da910426c8daf40994fde3a9ac3520.zip | |
ARM: Fix cases where CSI Restored bit is not cleared
LR is an untypical callee saved register in that it is restored into a
different register (PC) and thus does not live-out of the return block.
This case requires the `Restored` flag in CalleeSavedInfo to be cleared.
This fixes a number of cases where this wasn't handled correctly yet.
llvm-svn: 314471
Diffstat (limited to 'llvm/test/CodeGen/Thumb')
| -rw-r--r-- | llvm/test/CodeGen/Thumb/tbb-reuse.mir | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/llvm/test/CodeGen/Thumb/tbb-reuse.mir b/llvm/test/CodeGen/Thumb/tbb-reuse.mir index 15b9fa184c3..7d15c7c3ca7 100644 --- a/llvm/test/CodeGen/Thumb/tbb-reuse.mir +++ b/llvm/test/CodeGen/Thumb/tbb-reuse.mir @@ -93,7 +93,7 @@ frameInfo: hasVAStart: false hasMustTailInVarArgFunc: false stack: - - { id: 0, type: spill-slot, offset: -4, size: 4, alignment: 4, callee-saved-register: '%lr' } + - { id: 0, type: spill-slot, offset: -4, size: 4, alignment: 4, callee-saved-register: '%lr', callee-saved-restored: false } - { id: 1, type: spill-slot, offset: -8, size: 4, alignment: 4, callee-saved-register: '%r7' } jumpTable: kind: inline |
