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| author | Dan Gohman <gohman@apple.com> | 2010-01-21 02:09:26 +0000 |
|---|---|---|
| committer | Dan Gohman <gohman@apple.com> | 2010-01-21 02:09:26 +0000 |
| commit | 51ad99d2c514a8923a2519e37b43f774d95ef9a5 (patch) | |
| tree | 4dedf54ab5c92f08d11a647e31a5f249f3abf4fc /llvm/test/CodeGen/Thumb2/lsr-deficiency.ll | |
| parent | 626aba43d0960b8a99c1dd1680c866cc3f13bbf9 (diff) | |
| download | bcm5719-llvm-51ad99d2c514a8923a2519e37b43f774d95ef9a5.tar.gz bcm5719-llvm-51ad99d2c514a8923a2519e37b43f774d95ef9a5.zip | |
Re-implement the main strength-reduction portion of LoopStrengthReduction.
This new version is much more aggressive about doing "full" reduction in
cases where it reduces register pressure, and also more aggressive about
rewriting induction variables to count down (or up) to zero when doing so
reduces register pressure.
It currently uses fairly simplistic algorithms for finding reuse
opportunities, but it introduces a new framework allows it to combine
multiple strategies at once to form hybrid solutions, instead of doing
all full-reduction or all base+index.
llvm-svn: 94061
Diffstat (limited to 'llvm/test/CodeGen/Thumb2/lsr-deficiency.ll')
| -rw-r--r-- | llvm/test/CodeGen/Thumb2/lsr-deficiency.ll | 18 |
1 files changed, 11 insertions, 7 deletions
diff --git a/llvm/test/CodeGen/Thumb2/lsr-deficiency.ll b/llvm/test/CodeGen/Thumb2/lsr-deficiency.ll index 7b1b57a786e..ac2cd34e4b3 100644 --- a/llvm/test/CodeGen/Thumb2/lsr-deficiency.ll +++ b/llvm/test/CodeGen/Thumb2/lsr-deficiency.ll @@ -1,25 +1,29 @@ ; RUN: llc < %s -mtriple=thumbv7-apple-darwin10 -relocation-model=pic | FileCheck %s ; rdar://7387640 -; FIXME: We still need to rewrite array reference iv of stride -4 with loop -; count iv of stride -1. +; This now reduces to a single induction variable. + +; TODO: It still gets a GPR shuffle at the end of the loop +; This is because something in instruction selection has decided +; that comparing the pre-incremented value with zero is better +; than comparing the post-incremented value with -4. @G = external global i32 ; <i32*> [#uses=2] @array = external global i32* ; <i32**> [#uses=1] define arm_apcscc void @t() nounwind optsize { ; CHECK: t: -; CHECK: mov.w r2, #4000 -; CHECK: movw r3, #1001 +; CHECK: mov.w r2, #1000 entry: %.pre = load i32* @G, align 4 ; <i32> [#uses=1] br label %bb bb: ; preds = %bb, %entry ; CHECK: LBB1_1: -; CHECK: subs r3, #1 -; CHECK: cmp r3, #0 -; CHECK: sub.w r2, r2, #4 +; CHECK: cmp r2, #0 +; CHECK: sub.w r9, r2, #1 +; CHECK: mov r2, r9 + %0 = phi i32 [ %.pre, %entry ], [ %3, %bb ] ; <i32> [#uses=1] %indvar = phi i32 [ 0, %entry ], [ %indvar.next, %bb ] ; <i32> [#uses=2] %tmp5 = sub i32 1000, %indvar ; <i32> [#uses=1] |
