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| author | Sean Fertile <sfertile@ca.ibm.com> | 2016-11-14 18:43:59 +0000 |
|---|---|---|
| committer | Sean Fertile <sfertile@ca.ibm.com> | 2016-11-14 18:43:59 +0000 |
| commit | a435e07de85dfe6ef675aa584c6b074ea6cd98d7 (patch) | |
| tree | 76c9384c235fb8371ce38badc2ff5e72a1dbd95c /llvm/test/CodeGen/PowerPC | |
| parent | 544220fc0b31b4cc95aa183a20ef91922aeab7b7 (diff) | |
| download | bcm5719-llvm-a435e07de85dfe6ef675aa584c6b074ea6cd98d7.tar.gz bcm5719-llvm-a435e07de85dfe6ef675aa584c6b074ea6cd98d7.zip | |
[PPC] Add intrinsic mapping to the xscvhpsp instruction
add an intrinsic to expose the 'VSX Scalar Convert Half-Precision to
Single-Precision' instruction.
Differential review: https://reviews.llvm.org/D26536
llvm-svn: 286862
Diffstat (limited to 'llvm/test/CodeGen/PowerPC')
| -rw-r--r-- | llvm/test/CodeGen/PowerPC/vsx-p9.ll | 11 |
1 files changed, 11 insertions, 0 deletions
diff --git a/llvm/test/CodeGen/PowerPC/vsx-p9.ll b/llvm/test/CodeGen/PowerPC/vsx-p9.ll index 307859c7030..b2a496cbe60 100644 --- a/llvm/test/CodeGen/PowerPC/vsx-p9.ll +++ b/llvm/test/CodeGen/PowerPC/vsx-p9.ll @@ -331,4 +331,15 @@ entry: ; Function Attrs: nounwind readnone declare <2 x i64> @llvm.ppc.vsx.xvtstdcdp(<2 x double> %a, i32 %b) +define <4 x float> @testXVCVHPSP(<8 x i16> %a) { +entry: + %0 = tail call <4 x float>@llvm.ppc.vsx.xvcvhpsp(<8 x i16> %a) + ret <4 x float> %0 +; CHECK-LABEL: testXVCVHPSP +; CHECK: xvcvhpsp 34, 34 +; CHECK: blr +} +; Function Attrs: nounwind readnone +declare <4 x float>@llvm.ppc.vsx.xvcvhpsp(<8 x i16>) + declare void @sink(...) |
