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| author | Matthias Braun <matze@braunis.de> | 2016-08-24 22:34:06 +0000 |
|---|---|---|
| committer | Matthias Braun <matze@braunis.de> | 2016-08-24 22:34:06 +0000 |
| commit | a319e2cae0298cf710d65dc5c82cc1549b36658e (patch) | |
| tree | c797ceef43a23547b8ac09e53f476abe79ee0264 /llvm/test/CodeGen/PowerPC | |
| parent | 5dce48e0a707dfc0afa775e817c8ec0165404d02 (diff) | |
| download | bcm5719-llvm-a319e2cae0298cf710d65dc5c82cc1549b36658e.tar.gz bcm5719-llvm-a319e2cae0298cf710d65dc5c82cc1549b36658e.zip | |
MIRParser/MIRPrinter: Compute HasInlineAsm instead of printing/parsing it
llvm-svn: 279680
Diffstat (limited to 'llvm/test/CodeGen/PowerPC')
4 files changed, 0 insertions, 4 deletions
diff --git a/llvm/test/CodeGen/PowerPC/aantidep-def-ec.mir b/llvm/test/CodeGen/PowerPC/aantidep-def-ec.mir index 9e750eba280..a49251bde35 100644 --- a/llvm/test/CodeGen/PowerPC/aantidep-def-ec.mir +++ b/llvm/test/CodeGen/PowerPC/aantidep-def-ec.mir @@ -44,7 +44,6 @@ name: mm_update_next_owner alignment: 4 exposesReturnsTwice: false -hasInlineAsm: true allVRegsAllocated: true tracksRegLiveness: true liveins: diff --git a/llvm/test/CodeGen/PowerPC/addisdtprelha-nonr3.mir b/llvm/test/CodeGen/PowerPC/addisdtprelha-nonr3.mir index 0bf7b954f63..45ff51dc958 100644 --- a/llvm/test/CodeGen/PowerPC/addisdtprelha-nonr3.mir +++ b/llvm/test/CodeGen/PowerPC/addisdtprelha-nonr3.mir @@ -26,7 +26,6 @@ name: test1 alignment: 4 exposesReturnsTwice: false -hasInlineAsm: false allVRegsAllocated: true tracksRegLiveness: true frameInfo: diff --git a/llvm/test/CodeGen/PowerPC/no-rlwimi-trivial-commute.mir b/llvm/test/CodeGen/PowerPC/no-rlwimi-trivial-commute.mir index dce1e048a15..bab2ff22a4c 100644 --- a/llvm/test/CodeGen/PowerPC/no-rlwimi-trivial-commute.mir +++ b/llvm/test/CodeGen/PowerPC/no-rlwimi-trivial-commute.mir @@ -39,7 +39,6 @@ name: main alignment: 2 exposesReturnsTwice: false -hasInlineAsm: false tracksRegLiveness: true registers: - { id: 0, class: g8rc_and_g8rc_nox0 } diff --git a/llvm/test/CodeGen/PowerPC/opt-sub-inst-cr0-live.mir b/llvm/test/CodeGen/PowerPC/opt-sub-inst-cr0-live.mir index 619954effc2..d4b83b9a499 100644 --- a/llvm/test/CodeGen/PowerPC/opt-sub-inst-cr0-live.mir +++ b/llvm/test/CodeGen/PowerPC/opt-sub-inst-cr0-live.mir @@ -32,7 +32,6 @@ name: fn1 alignment: 2 exposesReturnsTwice: false -hasInlineAsm: false allVRegsAllocated: false tracksRegLiveness: true registers: |
