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| author | Carey Williams <carey.williams@arm.com> | 2018-01-22 14:16:11 +0000 |
|---|---|---|
| committer | Carey Williams <carey.williams@arm.com> | 2018-01-22 14:16:11 +0000 |
| commit | da15b5b1161b7f290f2b3cb30db7d6bc06fb83fb (patch) | |
| tree | 1a8afdba00241f67b91448ab63dd90dcc4c93ce5 /llvm/test/CodeGen/PowerPC/ctr-loop-tls-const.ll | |
| parent | 28d8a49f4276467e41ceec525b1cb2648f0ae653 (diff) | |
| download | bcm5719-llvm-da15b5b1161b7f290f2b3cb30db7d6bc06fb83fb.tar.gz bcm5719-llvm-da15b5b1161b7f290f2b3cb30db7d6bc06fb83fb.zip | |
[AArch64] optimise v4f16 fcmps to utilise vector instructions
Improves the code generation for v4f16 FCMP instructions when FullFP16 is not supported.
Generating FCTVL(s) rather than a longer series of FCVTs.
Differential Revision: https://reviews.llvm.org/D41772
llvm-svn: 323118
Diffstat (limited to 'llvm/test/CodeGen/PowerPC/ctr-loop-tls-const.ll')
0 files changed, 0 insertions, 0 deletions
