summaryrefslogtreecommitdiffstats
path: root/llvm/test/CodeGen/PowerPC/build-vector-tests.ll
diff options
context:
space:
mode:
authorTom Stellard <tstellar@redhat.com>2018-11-30 04:51:41 +0000
committerTom Stellard <tstellar@redhat.com>2018-11-30 04:51:41 +0000
commit4a6ae60f26152979c80137df145e834a889a64fc (patch)
tree6b95e448dd40f893c395665a6ee816ed00ed1ab9 /llvm/test/CodeGen/PowerPC/build-vector-tests.ll
parentd6ffc0c6ead2c0e94f7268b7270f30cc3f478f19 (diff)
downloadbcm5719-llvm-4a6ae60f26152979c80137df145e834a889a64fc.tar.gz
bcm5719-llvm-4a6ae60f26152979c80137df145e834a889a64fc.zip
Merging r339260:
------------------------------------------------------------------------ r339260 | syzaara | 2018-08-08 08:20:43 -0700 (Wed, 08 Aug 2018) | 13 lines [PowerPC] Improve codegen for vector loads using scalar_to_vector This patch aims to improve the codegen for vector loads involving the scalar_to_vector (load X) sequence. Initially, ld->mv instructions were used for scalar_to_vector (load X), so this patch allows scalar_to_vector (load X) to utilize: LXSD and LXSDX for i64 and f64 LXSIWAX for i32 (sign extension to i64) LXSIWZX for i32 and f64 Committing on behalf of Amy Kwan. Differential Revision: https://reviews.llvm.org/D48950 ------------------------------------------------------------------------ llvm-svn: 347957
Diffstat (limited to 'llvm/test/CodeGen/PowerPC/build-vector-tests.ll')
-rw-r--r--llvm/test/CodeGen/PowerPC/build-vector-tests.ll44
1 files changed, 28 insertions, 16 deletions
diff --git a/llvm/test/CodeGen/PowerPC/build-vector-tests.ll b/llvm/test/CodeGen/PowerPC/build-vector-tests.ll
index f074e2a0c0d..d192bafca23 100644
--- a/llvm/test/CodeGen/PowerPC/build-vector-tests.ll
+++ b/llvm/test/CodeGen/PowerPC/build-vector-tests.ll
@@ -109,8 +109,8 @@
;vector int spltRegVali(int val) { //
; return (vector int) val; //
;} //
-;// P8: lxsiwax, xxspltw //
-;// P9: lxvwsx //
+;// P8: (LE) lfiwzx, xxpermdi, xxspltw (BE): lfiwzx, xxsldwi, xxspltw //
+;// P9: (LE) lfiwzx, xxpermdi, xxspltw (BE): lfiwzx, xxsldwi, xxspltw //
;vector int spltMemVali(int *ptr) { //
; return (vector int)*ptr; //
;} //
@@ -284,8 +284,8 @@
;vector unsigned int spltRegValui(unsigned int val) { //
; return (vector unsigned int) val; //
;} //
-;// P8: lxsiwax, xxspltw //
-;// P9: lxvwsx //
+;// P8: (LE) lfiwzx, xxpermdi, xxspltw (BE): lfiwzx, xxsldwi, xxspltw //
+;// P9: (LE) lfiwzx, xxpermdi, xxspltw (BE): lfiwzx, xxsldwi, xxspltw //
;vector unsigned int spltMemValui(unsigned int *ptr) { //
; return (vector unsigned int)*ptr; //
;} //
@@ -1202,15 +1202,21 @@ entry:
; P9LE-LABEL: spltMemVali
; P8BE-LABEL: spltMemVali
; P8LE-LABEL: spltMemVali
-; P9BE: lxvwsx v2, 0, r3
+; P9BE: lfiwzx f0, 0, r3
+; P9BE: xxsldwi vs0, f0, f0, 1
+; P9BE: xxspltw v2, vs0, 0
; P9BE: blr
-; P9LE: lxvwsx v2, 0, r3
+; P9LE: lfiwzx f0, 0, r3
+; P9LE: xxpermdi vs0, f0, f0, 2
+; P9LE: xxspltw v2, vs0, 3
; P9LE: blr
-; P8BE: lxsiwax {{[vsf0-9]+}}, 0, r3
-; P8BE: xxspltw v2, {{[vsf0-9]+}}, 1
+; P8BE: lfiwzx f0, 0, r3
+; P8BE: xxsldwi vs0, f0, f0, 1
+; P8BE: xxspltw v2, vs0, 0
; P8BE: blr
-; P8LE: lxsiwax {{[vsf0-9]+}}, 0, r3
-; P8LE: xxspltw v2, {{[vsf0-9]+}}, 1
+; P8LE: lfiwzx f0, 0, r3
+; P8LE: xxpermdi vs0, f0, f0, 2
+; P8LE: xxspltw v2, vs0, 3
; P8LE: blr
}
@@ -2338,15 +2344,21 @@ entry:
; P9LE-LABEL: spltMemValui
; P8BE-LABEL: spltMemValui
; P8LE-LABEL: spltMemValui
-; P9BE: lxvwsx v2, 0, r3
+; P9BE: lfiwzx f0, 0, r3
+; P9BE: xxsldwi vs0, f0, f0, 1
+; P9BE: xxspltw v2, vs0, 0
; P9BE: blr
-; P9LE: lxvwsx v2, 0, r3
+; P9LE: lfiwzx f0, 0, r3
+; P9LE: xxpermdi vs0, f0, f0, 2
+; P9LE: xxspltw v2, vs0, 3
; P9LE: blr
-; P8BE: lxsiwax {{[vsf0-9]+}}, 0, r3
-; P8BE: xxspltw v2, {{[vsf0-9]+}}, 1
+; P8BE: lfiwzx f0, 0, r3
+; P8BE: xxsldwi vs0, f0, f0, 1
+; P8BE: xxspltw v2, vs0, 0
; P8BE: blr
-; P8LE: lxsiwax {{[vsf0-9]+}}, 0, r3
-; P8LE: xxspltw v2, {{[vsf0-9]+}}, 1
+; P8LE: lfiwzx f0, 0, r3
+; P8LE: xxpermdi vs0, f0, f0, 2
+; P8LE: xxspltw v2, vs0, 3
; P8LE: blr
}
OpenPOWER on IntegriCloud