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| author | Hiroshi Inoue <inouehrs@jp.ibm.com> | 2017-06-15 16:51:28 +0000 |
|---|---|---|
| committer | Hiroshi Inoue <inouehrs@jp.ibm.com> | 2017-06-15 16:51:28 +0000 |
| commit | 7a08bb145846730efc8a12ed1cb23a3534f30e72 (patch) | |
| tree | ec547a1dd1c279f70da79f14c38c5c5973028c13 /llvm/test/CodeGen/PowerPC/atomics-regression.ll | |
| parent | 24ca9da2dee135ef671f14707c709d17bd516498 (diff) | |
| download | bcm5719-llvm-7a08bb145846730efc8a12ed1cb23a3534f30e72.tar.gz bcm5719-llvm-7a08bb145846730efc8a12ed1cb23a3534f30e72.zip | |
[PowerPC] fix potential verification errors on CFENCE8
This patch fixes a potential verification error (64-bit register operands for cmpw) with -verify-machineinstrs.
Differential Revision: https://reviews.llvm.org/D34208
llvm-svn: 305479
Diffstat (limited to 'llvm/test/CodeGen/PowerPC/atomics-regression.ll')
| -rw-r--r-- | llvm/test/CodeGen/PowerPC/atomics-regression.ll | 20 |
1 files changed, 10 insertions, 10 deletions
diff --git a/llvm/test/CodeGen/PowerPC/atomics-regression.ll b/llvm/test/CodeGen/PowerPC/atomics-regression.ll index 054d3a4146b..d57b3a20379 100644 --- a/llvm/test/CodeGen/PowerPC/atomics-regression.ll +++ b/llvm/test/CodeGen/PowerPC/atomics-regression.ll @@ -23,7 +23,7 @@ define i8 @test2(i8* %ptr) { ; PPC64LE-LABEL: test2: ; PPC64LE: # BB#0: ; PPC64LE-NEXT: lbz 3, 0(3) -; PPC64LE-NEXT: cmpw 7, 3, 3 +; PPC64LE-NEXT: cmpd 7, 3, 3 ; PPC64LE-NEXT: bne- 7, .+4 ; PPC64LE-NEXT: isync ; PPC64LE-NEXT: blr @@ -37,7 +37,7 @@ define i8 @test3(i8* %ptr) { ; PPC64LE-NEXT: sync ; PPC64LE-NEXT: ori 2, 2, 0 ; PPC64LE-NEXT: lbz 3, 0(3) -; PPC64LE-NEXT: cmpw 7, 3, 3 +; PPC64LE-NEXT: cmpd 7, 3, 3 ; PPC64LE-NEXT: bne- 7, .+4 ; PPC64LE-NEXT: isync ; PPC64LE-NEXT: blr @@ -67,7 +67,7 @@ define i16 @test6(i16* %ptr) { ; PPC64LE-LABEL: test6: ; PPC64LE: # BB#0: ; PPC64LE-NEXT: lhz 3, 0(3) -; PPC64LE-NEXT: cmpw 7, 3, 3 +; PPC64LE-NEXT: cmpd 7, 3, 3 ; PPC64LE-NEXT: bne- 7, .+4 ; PPC64LE-NEXT: isync ; PPC64LE-NEXT: blr @@ -81,7 +81,7 @@ define i16 @test7(i16* %ptr) { ; PPC64LE-NEXT: sync ; PPC64LE-NEXT: ori 2, 2, 0 ; PPC64LE-NEXT: lhz 3, 0(3) -; PPC64LE-NEXT: cmpw 7, 3, 3 +; PPC64LE-NEXT: cmpd 7, 3, 3 ; PPC64LE-NEXT: bne- 7, .+4 ; PPC64LE-NEXT: isync ; PPC64LE-NEXT: blr @@ -111,7 +111,7 @@ define i32 @test10(i32* %ptr) { ; PPC64LE-LABEL: test10: ; PPC64LE: # BB#0: ; PPC64LE-NEXT: lwz 3, 0(3) -; PPC64LE-NEXT: cmpw 7, 3, 3 +; PPC64LE-NEXT: cmpd 7, 3, 3 ; PPC64LE-NEXT: bne- 7, .+4 ; PPC64LE-NEXT: isync ; PPC64LE-NEXT: blr @@ -125,7 +125,7 @@ define i32 @test11(i32* %ptr) { ; PPC64LE-NEXT: sync ; PPC64LE-NEXT: ori 2, 2, 0 ; PPC64LE-NEXT: lwz 3, 0(3) -; PPC64LE-NEXT: cmpw 7, 3, 3 +; PPC64LE-NEXT: cmpd 7, 3, 3 ; PPC64LE-NEXT: bne- 7, .+4 ; PPC64LE-NEXT: isync ; PPC64LE-NEXT: blr @@ -155,7 +155,7 @@ define i64 @test14(i64* %ptr) { ; PPC64LE-LABEL: test14: ; PPC64LE: # BB#0: ; PPC64LE-NEXT: ld 3, 0(3) -; PPC64LE-NEXT: cmpw 7, 3, 3 +; PPC64LE-NEXT: cmpd 7, 3, 3 ; PPC64LE-NEXT: bne- 7, .+4 ; PPC64LE-NEXT: isync ; PPC64LE-NEXT: blr @@ -169,7 +169,7 @@ define i64 @test15(i64* %ptr) { ; PPC64LE-NEXT: sync ; PPC64LE-NEXT: ori 2, 2, 0 ; PPC64LE-NEXT: ld 3, 0(3) -; PPC64LE-NEXT: cmpw 7, 3, 3 +; PPC64LE-NEXT: cmpd 7, 3, 3 ; PPC64LE-NEXT: bne- 7, .+4 ; PPC64LE-NEXT: isync ; PPC64LE-NEXT: blr @@ -9566,7 +9566,7 @@ define i32 @test_ordering0(i32* %ptr1, i32* %ptr2) { ; PPC64LE-LABEL: test_ordering0: ; PPC64LE: # BB#0: ; PPC64LE-NEXT: lwz 4, 0(3) -; PPC64LE-NEXT: cmpw 7, 4, 4 +; PPC64LE-NEXT: cmpd 7, 4, 4 ; PPC64LE-NEXT: bne- 7, .+4 ; PPC64LE-NEXT: isync ; PPC64LE-NEXT: lwz 3, 0(3) @@ -9583,7 +9583,7 @@ define i32 @test_ordering1(i32* %ptr1, i32 %val1, i32* %ptr2) { ; PPC64LE-LABEL: test_ordering1: ; PPC64LE: # BB#0: ; PPC64LE-NEXT: lwz 3, 0(3) -; PPC64LE-NEXT: cmpw 7, 3, 3 +; PPC64LE-NEXT: cmpd 7, 3, 3 ; PPC64LE-NEXT: bne- 7, .+4 ; PPC64LE-NEXT: isync ; PPC64LE-NEXT: stw 4, 0(5) |
