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| author | Nirav Dave <niravd@google.com> | 2018-10-11 18:28:59 +0000 |
|---|---|---|
| committer | Nirav Dave <niravd@google.com> | 2018-10-11 18:28:59 +0000 |
| commit | f1f2a2a31ad6200f468718dbbc75fbfbea152915 (patch) | |
| tree | 701149a189faff780647fb2235db0f5572ce8926 /llvm/test/CodeGen/Mips/cconv | |
| parent | 5d3a6f76a8d642e81399e64606152d9f34d6e751 (diff) | |
| download | bcm5719-llvm-f1f2a2a31ad6200f468718dbbc75fbfbea152915.tar.gz bcm5719-llvm-f1f2a2a31ad6200f468718dbbc75fbfbea152915.zip | |
[DAG] Fix Big Endian in Load-Store forwarding
Summary:
Correct offset calculation in load-store forwarding for big-endian
targets.
Reviewers: rnk, RKSimon, waltl
Subscribers: sdardis, nemanjai, hiraditya, jrtc27, atanasyan, jsji, llvm-commits
Differential Revision: https://reviews.llvm.org/D53147
llvm-svn: 344272
Diffstat (limited to 'llvm/test/CodeGen/Mips/cconv')
| -rw-r--r-- | llvm/test/CodeGen/Mips/cconv/vector.ll | 70 |
1 files changed, 47 insertions, 23 deletions
diff --git a/llvm/test/CodeGen/Mips/cconv/vector.ll b/llvm/test/CodeGen/Mips/cconv/vector.ll index 8cec16683ca..29ffe23f712 100644 --- a/llvm/test/CodeGen/Mips/cconv/vector.ll +++ b/llvm/test/CodeGen/Mips/cconv/vector.ll @@ -2045,29 +2045,29 @@ define <2 x i32> @i32_2(<2 x i32> %a, <2 x i32> %b) { ; MIPS32R5EB-NEXT: jr $ra ; MIPS32R5EB-NEXT: nop ; -; MIPS64R5-LABEL: i32_2: -; MIPS64R5: # %bb.0: -; MIPS64R5-NEXT: daddiu $sp, $sp, -32 -; MIPS64R5-NEXT: .cfi_def_cfa_offset 32 -; MIPS64R5-NEXT: sd $5, 16($sp) -; MIPS64R5-NEXT: sd $4, 24($sp) -; MIPS64R5-NEXT: ldi.b $w0, 0 -; MIPS64R5-NEXT: lw $1, 20($sp) -; MIPS64R5-NEXT: move.v $w1, $w0 -; MIPS64R5-NEXT: insert.d $w1[0], $5 -; MIPS64R5-NEXT: insert.d $w1[1], $1 -; MIPS64R5-NEXT: insert.d $w0[0], $4 -; MIPS64R5-NEXT: lw $1, 28($sp) -; MIPS64R5-NEXT: insert.d $w0[1], $1 -; MIPS64R5-NEXT: addv.d $w0, $w0, $w1 -; MIPS64R5-NEXT: copy_s.d $1, $w0[0] -; MIPS64R5-NEXT: copy_s.d $2, $w0[1] -; MIPS64R5-NEXT: sw $2, 12($sp) -; MIPS64R5-NEXT: sw $1, 8($sp) -; MIPS64R5-NEXT: ld $2, 8($sp) -; MIPS64R5-NEXT: daddiu $sp, $sp, 32 -; MIPS64R5-NEXT: jr $ra -; MIPS64R5-NEXT: nop +; MIPS64R5EB-LABEL: i32_2: +; MIPS64R5EB: # %bb.0: +; MIPS64R5EB-NEXT: daddiu $sp, $sp, -32 +; MIPS64R5EB-NEXT: .cfi_def_cfa_offset 32 +; MIPS64R5EB-NEXT: sd $5, 16($sp) +; MIPS64R5EB-NEXT: sd $4, 24($sp) +; MIPS64R5EB-NEXT: ldi.b $w0, 0 +; MIPS64R5EB-NEXT: lw $1, 16($sp) +; MIPS64R5EB-NEXT: move.v $w1, $w0 +; MIPS64R5EB-NEXT: insert.d $w1[0], $1 +; MIPS64R5EB-NEXT: insert.d $w1[1], $5 +; MIPS64R5EB-NEXT: lw $1, 24($sp) +; MIPS64R5EB-NEXT: insert.d $w0[0], $1 +; MIPS64R5EB-NEXT: insert.d $w0[1], $4 +; MIPS64R5EB-NEXT: addv.d $w0, $w0, $w1 +; MIPS64R5EB-NEXT: copy_s.d $1, $w0[0] +; MIPS64R5EB-NEXT: copy_s.d $2, $w0[1] +; MIPS64R5EB-NEXT: sw $2, 12($sp) +; MIPS64R5EB-NEXT: sw $1, 8($sp) +; MIPS64R5EB-NEXT: ld $2, 8($sp) +; MIPS64R5EB-NEXT: daddiu $sp, $sp, 32 +; MIPS64R5EB-NEXT: jr $ra +; MIPS64R5EB-NEXT: nop ; ; MIPS32R5EL-LABEL: i32_2: ; MIPS32R5EL: # %bb.0: @@ -2093,6 +2093,30 @@ define <2 x i32> @i32_2(<2 x i32> %a, <2 x i32> %b) { ; MIPS32R5EL-NEXT: addiu $sp, $sp, 48 ; MIPS32R5EL-NEXT: jr $ra ; MIPS32R5EL-NEXT: nop +; +; MIPS64R5EL-LABEL: i32_2: +; MIPS64R5EL: # %bb.0: +; MIPS64R5EL-NEXT: daddiu $sp, $sp, -32 +; MIPS64R5EL-NEXT: .cfi_def_cfa_offset 32 +; MIPS64R5EL-NEXT: sd $5, 16($sp) +; MIPS64R5EL-NEXT: sd $4, 24($sp) +; MIPS64R5EL-NEXT: ldi.b $w0, 0 +; MIPS64R5EL-NEXT: lw $1, 20($sp) +; MIPS64R5EL-NEXT: move.v $w1, $w0 +; MIPS64R5EL-NEXT: insert.d $w1[0], $5 +; MIPS64R5EL-NEXT: insert.d $w1[1], $1 +; MIPS64R5EL-NEXT: insert.d $w0[0], $4 +; MIPS64R5EL-NEXT: lw $1, 28($sp) +; MIPS64R5EL-NEXT: insert.d $w0[1], $1 +; MIPS64R5EL-NEXT: addv.d $w0, $w0, $w1 +; MIPS64R5EL-NEXT: copy_s.d $1, $w0[0] +; MIPS64R5EL-NEXT: copy_s.d $2, $w0[1] +; MIPS64R5EL-NEXT: sw $2, 12($sp) +; MIPS64R5EL-NEXT: sw $1, 8($sp) +; MIPS64R5EL-NEXT: ld $2, 8($sp) +; MIPS64R5EL-NEXT: daddiu $sp, $sp, 32 +; MIPS64R5EL-NEXT: jr $ra +; MIPS64R5EL-NEXT: nop %1 = add <2 x i32> %a, %b ret <2 x i32> %1 } |
