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| author | Craig Topper <craig.topper@intel.com> | 2018-08-28 03:47:20 +0000 |
|---|---|---|
| committer | Craig Topper <craig.topper@intel.com> | 2018-08-28 03:47:20 +0000 |
| commit | c7506b28c11b4a382bd499c21ef5e6aac8c3c29f (patch) | |
| tree | e852db7f307fc70d417f2860cf978d5e18a0b7f8 /llvm/test/CodeGen/Mips/cconv | |
| parent | a6cd4b9bced862533d5ce7ca4dde18d82b623801 (diff) | |
| download | bcm5719-llvm-c7506b28c11b4a382bd499c21ef5e6aac8c3c29f.tar.gz bcm5719-llvm-c7506b28c11b4a382bd499c21ef5e6aac8c3c29f.zip | |
[DAGCombiner][AMDGPU][Mips] Fold bitcast with volatile loads if the resulting load is legal for the target.
Summary:
I'm not sure if this patch is correct or if it needs more qualifying somehow. Bitcast shouldn't change the size of the load so it should be ok? We already do something similar for stores. We'll change the type of a volatile store if the resulting store is Legal or Custom. I'm not sure we should be allowing Custom there...
I was playing around with converting X86 atomic loads/stores(except seq_cst) into regular volatile loads and stores during lowering. This would allow some special RMW isel patterns in X86InstrCompiler.td to be removed. But there's some floating point patterns in there that didn't work because we don't fold (f64 (bitconvert (i64 volatile load))) or (f32 (bitconvert (i32 volatile load))).
Reviewers: efriedma, atanasyan, arsenm
Reviewed By: efriedma
Subscribers: jvesely, arsenm, sdardis, kzhuravl, wdng, yaxunl, dstuttard, tpr, t-tye, arichardson, jrtc27, atanasyan, jfb, llvm-commits
Differential Revision: https://reviews.llvm.org/D50491
llvm-svn: 340797
Diffstat (limited to 'llvm/test/CodeGen/Mips/cconv')
| -rw-r--r-- | llvm/test/CodeGen/Mips/cconv/return-hard-fp128.ll | 12 | ||||
| -rw-r--r-- | llvm/test/CodeGen/Mips/cconv/return-hard-struct-f128.ll | 12 |
2 files changed, 8 insertions, 16 deletions
diff --git a/llvm/test/CodeGen/Mips/cconv/return-hard-fp128.ll b/llvm/test/CodeGen/Mips/cconv/return-hard-fp128.ll index e527866eb97..ca0794b22dc 100644 --- a/llvm/test/CodeGen/Mips/cconv/return-hard-fp128.ll +++ b/llvm/test/CodeGen/Mips/cconv/return-hard-fp128.ll @@ -18,14 +18,10 @@ entry: } ; ALL-LABEL: retldouble: -; N32-DAG: ld [[R2:\$[0-9]+]], %lo(fp128)([[R1:\$[0-9]+]]) +; N32-DAG: ldc1 $f0, %lo(fp128)([[R1:\$[0-9]+]]) ; N32-DAG: addiu [[R3:\$[0-9]+]], [[R1]], %lo(fp128) -; N32-DAG: ld [[R4:\$[0-9]+]], 8([[R3]]) -; N32-DAG: dmtc1 [[R2]], $f0 -; N32-DAG: dmtc1 [[R4]], $f2 +; N32-DAG: ldc1 $f2, 8([[R3]]) ; N64-DAG: lui [[R2:\$[0-9]+]], %highest(fp128) -; N64-DAG: ld [[R3:\$[0-9]+]], %lo(fp128)([[R2]]) -; N64-DAG: ld [[R4:\$[0-9]+]], 8([[R2]]) -; N64-DAG: dmtc1 [[R3]], $f0 -; N64-DAG: dmtc1 [[R4]], $f2 +; N64-DAG: ldc1 $f0, %lo(fp128)([[R2]]) +; N64-DAG: ldc1 $f2, 8([[R2]]) diff --git a/llvm/test/CodeGen/Mips/cconv/return-hard-struct-f128.ll b/llvm/test/CodeGen/Mips/cconv/return-hard-struct-f128.ll index 492db768950..43b0baa7001 100644 --- a/llvm/test/CodeGen/Mips/cconv/return-hard-struct-f128.ll +++ b/llvm/test/CodeGen/Mips/cconv/return-hard-struct-f128.ll @@ -23,14 +23,10 @@ entry: ; is returned in $f0, and $f1 instead of the usual $f0, and $f2. This is to ; match the de facto ABI as implemented by GCC. ; N32-DAG: lui [[R1:\$[0-9]+]], %hi(struct_fp128) -; N32-DAG: ld [[R2:\$[0-9]+]], %lo(struct_fp128)([[R1]]) -; N32-DAG: dmtc1 [[R2]], $f0 +; N32-DAG: ldc1 $f0, %lo(struct_fp128)([[R1]]) ; N32-DAG: addiu [[R3:\$[0-9]+]], [[R1]], %lo(struct_fp128) -; N32-DAG: ld [[R4:\$[0-9]+]], 8([[R3]]) -; N32-DAG: dmtc1 [[R4]], $f1 +; N32-DAG: ldc1 $f1, 8([[R3]]) ; N64-DAG: lui [[R1:\$[0-9]+]], %highest(struct_fp128) -; N64-DAG: ld [[R2:\$[0-9]+]], %lo(struct_fp128)([[R1]]) -; N64-DAG: dmtc1 [[R2]], $f0 -; N64-DAG: ld [[R4:\$[0-9]+]], 8([[R1]]) -; N64-DAG: dmtc1 [[R4]], $f1 +; N64-DAG: ldc1 $f0, %lo(struct_fp128)([[R1]]) +; N64-DAG: ldc1 $f1, 8([[R1]]) |
