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| author | Nirav Dave <niravd@google.com> | 2018-10-10 14:15:52 +0000 |
|---|---|---|
| committer | Nirav Dave <niravd@google.com> | 2018-10-10 14:15:52 +0000 |
| commit | 07acc992dc39edfccc5a4b773c3dcf8a5bf6d893 (patch) | |
| tree | 3bf75667e8a6457c656e5eac1ca0dd14c12ff32a /llvm/test/CodeGen/Mips/cconv | |
| parent | 6cca8af2270be8bc5494b44bb8856af591d0385b (diff) | |
| download | bcm5719-llvm-07acc992dc39edfccc5a4b773c3dcf8a5bf6d893.tar.gz bcm5719-llvm-07acc992dc39edfccc5a4b773c3dcf8a5bf6d893.zip | |
[DAGCombine] Improve Load-Store Forwarding
Summary:
Extend analysis forwarding loads from preceeding stores to work with
extended loads and truncated stores to the same address so long as the
load is fully subsumed by the store.
Hexagon's swp-epilog-phis.ll and swp-memrefs-epilog1.ll test are
deleted as they've no longer seem to be relevant.
Reviewers: RKSimon, rnk, kparzysz, javed.absar
Subscribers: sdardis, nemanjai, hiraditya, atanasyan, llvm-commits
Differential Revision: https://reviews.llvm.org/D49200
llvm-svn: 344142
Diffstat (limited to 'llvm/test/CodeGen/Mips/cconv')
| -rw-r--r-- | llvm/test/CodeGen/Mips/cconv/vector.ll | 22 |
1 files changed, 6 insertions, 16 deletions
diff --git a/llvm/test/CodeGen/Mips/cconv/vector.ll b/llvm/test/CodeGen/Mips/cconv/vector.ll index b580d2a338c..8cec16683ca 100644 --- a/llvm/test/CodeGen/Mips/cconv/vector.ll +++ b/llvm/test/CodeGen/Mips/cconv/vector.ll @@ -2053,12 +2053,10 @@ define <2 x i32> @i32_2(<2 x i32> %a, <2 x i32> %b) { ; MIPS64R5-NEXT: sd $4, 24($sp) ; MIPS64R5-NEXT: ldi.b $w0, 0 ; MIPS64R5-NEXT: lw $1, 20($sp) -; MIPS64R5-NEXT: lw $2, 16($sp) ; MIPS64R5-NEXT: move.v $w1, $w0 -; MIPS64R5-NEXT: insert.d $w1[0], $2 +; MIPS64R5-NEXT: insert.d $w1[0], $5 ; MIPS64R5-NEXT: insert.d $w1[1], $1 -; MIPS64R5-NEXT: lw $1, 24($sp) -; MIPS64R5-NEXT: insert.d $w0[0], $1 +; MIPS64R5-NEXT: insert.d $w0[0], $4 ; MIPS64R5-NEXT: lw $1, 28($sp) ; MIPS64R5-NEXT: insert.d $w0[1], $1 ; MIPS64R5-NEXT: addv.d $w0, $w0, $w1 @@ -3533,12 +3531,8 @@ define void @call_i8_2() { ; MIPS32R5EB-NEXT: .cfi_def_cfa_offset 32 ; MIPS32R5EB-NEXT: sw $ra, 28($sp) # 4-byte Folded Spill ; MIPS32R5EB-NEXT: .cfi_offset 31, -4 -; MIPS32R5EB-NEXT: addiu $1, $zero, 1543 -; MIPS32R5EB-NEXT: sh $1, 20($sp) -; MIPS32R5EB-NEXT: addiu $1, $zero, 3080 -; MIPS32R5EB-NEXT: sh $1, 24($sp) -; MIPS32R5EB-NEXT: lhu $4, 20($sp) -; MIPS32R5EB-NEXT: lhu $5, 24($sp) +; MIPS32R5EB-NEXT: addiu $4, $zero, 1543 +; MIPS32R5EB-NEXT: addiu $5, $zero, 3080 ; MIPS32R5EB-NEXT: jal i8_2 ; MIPS32R5EB-NEXT: nop ; MIPS32R5EB-NEXT: sw $2, 16($sp) @@ -3645,12 +3639,8 @@ define void @call_i8_2() { ; MIPS32R5EL-NEXT: .cfi_def_cfa_offset 32 ; MIPS32R5EL-NEXT: sw $ra, 28($sp) # 4-byte Folded Spill ; MIPS32R5EL-NEXT: .cfi_offset 31, -4 -; MIPS32R5EL-NEXT: addiu $1, $zero, 1798 -; MIPS32R5EL-NEXT: sh $1, 20($sp) -; MIPS32R5EL-NEXT: addiu $1, $zero, 2060 -; MIPS32R5EL-NEXT: sh $1, 24($sp) -; MIPS32R5EL-NEXT: lhu $4, 20($sp) -; MIPS32R5EL-NEXT: lhu $5, 24($sp) +; MIPS32R5EL-NEXT: addiu $4, $zero, 1798 +; MIPS32R5EL-NEXT: addiu $5, $zero, 2060 ; MIPS32R5EL-NEXT: jal i8_2 ; MIPS32R5EL-NEXT: nop ; MIPS32R5EL-NEXT: sw $2, 16($sp) |
