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| author | Tim Northover <tnorthover@apple.com> | 2015-12-02 18:12:57 +0000 |
|---|---|---|
| committer | Tim Northover <tnorthover@apple.com> | 2015-12-02 18:12:57 +0000 |
| commit | f520eff7827912ab1f9aa2dd08fcd2b0bfa4f945 (patch) | |
| tree | 34caa0a7a53260c2d71ff91ae7ad0db1031464ec /llvm/test/CodeGen/ARM | |
| parent | 53d13997925027af4e1d70d314d6bcb0b159672b (diff) | |
| download | bcm5719-llvm-f520eff7827912ab1f9aa2dd08fcd2b0bfa4f945.tar.gz bcm5719-llvm-f520eff7827912ab1f9aa2dd08fcd2b0bfa4f945.zip | |
AArch64: use ldxp/stxp pair to implement 128-bit atomic loads.
The ARM ARM is clear that 128-bit loads are only guaranteed to have been atomic
if there has been a corresponding successful stxp. It's less clear for AArch32, so
I'm leaving that alone for now.
llvm-svn: 254524
Diffstat (limited to 'llvm/test/CodeGen/ARM')
| -rw-r--r-- | llvm/test/CodeGen/ARM/atomic-64bit.ll | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/llvm/test/CodeGen/ARM/atomic-64bit.ll b/llvm/test/CodeGen/ARM/atomic-64bit.ll index 7510d6ccdc3..573cd45c082 100644 --- a/llvm/test/CodeGen/ARM/atomic-64bit.ll +++ b/llvm/test/CodeGen/ARM/atomic-64bit.ll @@ -208,10 +208,16 @@ define i64 @test7(i64* %ptr, i64 %val1, i64 %val2) { define i64 @test8(i64* %ptr) { ; CHECK-LABEL: test8: ; CHECK: ldrexd [[REG1:(r[0-9]?[02468])]], [[REG2:(r[0-9]?[13579])]] +; CHECK-NOT: strexd +; CHECK: clrex +; CHECK-NOT: strexd ; CHECK: dmb {{ish$}} ; CHECK-THUMB-LABEL: test8: ; CHECK-THUMB: ldrexd [[REG1:[a-z0-9]+]], [[REG2:[a-z0-9]+]] +; CHECK-THUMB-NOT: strexd +; CHECK-THUMB: clrex +; CHECK-THUMB-NOT: strexd ; CHECK-THUMB: dmb {{ish$}} %r = load atomic i64, i64* %ptr seq_cst, align 8 |
