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| author | Simon Pilgrim <llvm-dev@redking.me.uk> | 2020-01-04 13:15:50 +0000 |
|---|---|---|
| committer | Simon Pilgrim <llvm-dev@redking.me.uk> | 2020-01-04 13:15:50 +0000 |
| commit | eb0e1978df7b9e7df3e645bb48fbf655f8aab69a (patch) | |
| tree | e410d5a72291fca50a9ce6248a587b0f294bb457 /llvm/test/CodeGen/ARM | |
| parent | 1737cc750c464b454ec14b397ce1b7cf504e17a7 (diff) | |
| download | bcm5719-llvm-eb0e1978df7b9e7df3e645bb48fbf655f8aab69a.tar.gz bcm5719-llvm-eb0e1978df7b9e7df3e645bb48fbf655f8aab69a.zip | |
[TargetLowering] SimplifyDemandedBits - call SimplifyMultipleUseDemandedBits for ISD::EXTRACT_VECTOR_ELT (REAPPLIED)
This patch attempts to peek through vectors based on the demanded bits/elt of a particular ISD::EXTRACT_VECTOR_ELT node, allowing us to avoid dependencies on ops that have no impact on the extract.
In particular this helps remove some unnecessary scalar->vector->scalar patterns.
The wasm shift patterns are annoying - @tlively has indicated that the wasm vector shift codegen are to be refactored in the near-term and isn't considered a major issue.
Reapplied after reversion at rL368660 due to PR42982 which was fixed at rGca7fdd41bda0.
Differential Revision: https://reviews.llvm.org/D65887
Diffstat (limited to 'llvm/test/CodeGen/ARM')
| -rw-r--r-- | llvm/test/CodeGen/ARM/dagcombine-anyexttozeroext.ll | 9 |
1 files changed, 3 insertions, 6 deletions
diff --git a/llvm/test/CodeGen/ARM/dagcombine-anyexttozeroext.ll b/llvm/test/CodeGen/ARM/dagcombine-anyexttozeroext.ll index de24681470d..643468c6dc8 100644 --- a/llvm/test/CodeGen/ARM/dagcombine-anyexttozeroext.ll +++ b/llvm/test/CodeGen/ARM/dagcombine-anyexttozeroext.ll @@ -113,17 +113,14 @@ define float @k(<8 x i8>* nocapture %in) { } define float @KnownUpperZero(<4 x i16> %v) { -; FIXME: uxtb are not required ; CHECK-LABEL: KnownUpperZero: ; CHECK: @ %bb.0: -; CHECK-NEXT: vmov.i16 d16, #0x3 -; CHECK-NEXT: vmov d17, r0, r1 -; CHECK-NEXT: vand d16, d17, d16 +; CHECK-NEXT: vmov d16, r0, r1 ; CHECK-NEXT: vmov.u16 r0, d16[0] ; CHECK-NEXT: vmov.u16 r1, d16[3] -; CHECK-NEXT: uxtb r0, r0 +; CHECK-NEXT: and r0, r0, #3 ; CHECK-NEXT: vmov s0, r0 -; CHECK-NEXT: uxtb r0, r1 +; CHECK-NEXT: and r0, r1, #3 ; CHECK-NEXT: vmov s2, r0 ; CHECK-NEXT: vcvt.f32.s32 s0, s0 ; CHECK-NEXT: vcvt.f32.s32 s2, s2 |
