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| author | Evan Cheng <evan.cheng@apple.com> | 2011-01-21 18:55:51 +0000 |
|---|---|---|
| committer | Evan Cheng <evan.cheng@apple.com> | 2011-01-21 18:55:51 +0000 |
| commit | 2f2435d026fdc8259048fdd03156ec6f119d9d9c (patch) | |
| tree | 1f42084b928400dca86820e79879be55c6c0ce33 /llvm/test/CodeGen/ARM/machine-licm.ll | |
| parent | 83758d5cd7e196bb7be784d38f9c00ea501654ca (diff) | |
| download | bcm5719-llvm-2f2435d026fdc8259048fdd03156ec6f119d9d9c.tar.gz bcm5719-llvm-2f2435d026fdc8259048fdd03156ec6f119d9d9c.zip | |
Last round of fixes for movw + movt global address codegen.
1. Fixed ARM pc adjustment.
2. Fixed dynamic-no-pic codegen
3. CSE of pc-relative load of global addresses.
It's now enabled by default for Darwin.
llvm-svn: 123991
Diffstat (limited to 'llvm/test/CodeGen/ARM/machine-licm.ll')
| -rw-r--r-- | llvm/test/CodeGen/ARM/machine-licm.ll | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/llvm/test/CodeGen/ARM/machine-licm.ll b/llvm/test/CodeGen/ARM/machine-licm.ll index a0494134f06..8656c5bbd72 100644 --- a/llvm/test/CodeGen/ARM/machine-licm.ll +++ b/llvm/test/CodeGen/ARM/machine-licm.ll @@ -1,6 +1,6 @@ ; RUN: llc < %s -mtriple=thumb-apple-darwin -relocation-model=pic -disable-fp-elim | FileCheck %s -check-prefix=THUMB ; RUN: llc < %s -mtriple=arm-apple-darwin -relocation-model=pic -disable-fp-elim | FileCheck %s -check-prefix=ARM -; RUN: llc < %s -mtriple=armv7-apple-darwin10 -relocation-model=pic -disable-fp-elim -arm-darwin-use-movt | FileCheck %s -check-prefix=MOVT +; RUN: llc < %s -mtriple=arm-apple-darwin -relocation-model=pic -disable-fp-elim -mattr=+v6t2 | FileCheck %s -check-prefix=MOVT ; rdar://7353541 ; rdar://7354376 ; rdar://8887598 @@ -24,8 +24,8 @@ entry: ; ARM: ldr r{{[0-9]+}}, [r{{[0-9]+}}] ; MOVT: t: -; MOVT: movw [[REGISTER_2:r[0-9]+]], :lower16:(L_GV$non_lazy_ptr-(LPC0_0+4)) -; MOVT: movt [[REGISTER_2]], :upper16:(L_GV$non_lazy_ptr-(LPC0_0+4)) +; MOVT: movw [[REGISTER_2:r[0-9]+]], :lower16:(L_GV$non_lazy_ptr-(LPC0_0+8)) +; MOVT: movt [[REGISTER_2]], :upper16:(L_GV$non_lazy_ptr-(LPC0_0+8)) ; MOVT: LPC0_0: ; MOVT: ldr r{{[0-9]+}}, [pc, [[REGISTER_2]]] ; MOVT: ldr r{{[0-9]+}}, [r{{[0-9]+}}] |
