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| author | Matt Arsenault <Matthew.Arsenault@amd.com> | 2019-03-08 20:30:50 +0000 |
|---|---|---|
| committer | Matt Arsenault <Matthew.Arsenault@amd.com> | 2019-03-08 20:30:50 +0000 |
| commit | 07f904befba01b4d7f7ec9d5b1c70e20c6dcbd7d (patch) | |
| tree | 25fd7feed18946d09b607d3c20ae908850c41f69 /llvm/test/CodeGen/AMDGPU | |
| parent | 94b575b23bded5067ad6ba254be3f53b98ed7c6a (diff) | |
| download | bcm5719-llvm-07f904befba01b4d7f7ec9d5b1c70e20c6dcbd7d.tar.gz bcm5719-llvm-07f904befba01b4d7f7ec9d5b1c70e20c6dcbd7d.zip | |
AMDGPU: Correct DS implementation of areLoadsFromSameBasePtr
This was checking the wrong operands for the base register and the
offsets. The indexes are shifted by the number of output registers
from the machine instruction definition, and the chain is moved to the
end.
llvm-svn: 355722
Diffstat (limited to 'llvm/test/CodeGen/AMDGPU')
| -rw-r--r-- | llvm/test/CodeGen/AMDGPU/ds-combine-with-dependence.ll | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/llvm/test/CodeGen/AMDGPU/ds-combine-with-dependence.ll b/llvm/test/CodeGen/AMDGPU/ds-combine-with-dependence.ll index 06fa048124a..ba7c0f3983c 100644 --- a/llvm/test/CodeGen/AMDGPU/ds-combine-with-dependence.ll +++ b/llvm/test/CodeGen/AMDGPU/ds-combine-with-dependence.ll @@ -6,8 +6,8 @@ ; GCN-LABEL: {{^}}ds_combine_nodep -; GCN: ds_write2_b32 v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}} offset0:26 offset1:27 -; GCN-NEXT: ds_read2_b32 v{{\[[0-9]+:[0-9]+\]}}, v{{[0-9]+}} offset0:7 offset1:8 +; GCN: ds_read2_b32 v{{\[[0-9]+:[0-9]+\]}}, v{{[0-9]+}} offset0:7 offset1:8 +; GCN-NEXT: ds_write2_b32 v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}} offset0:26 offset1:27 define amdgpu_kernel void @ds_combine_nodep(float addrspace(1)* %out, float addrspace(3)* %inptr) { %base = bitcast float addrspace(3)* %inptr to i8 addrspace(3)* |
