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| author | Mark Searles <m.c.searles@gmail.com> | 2017-06-02 14:19:25 +0000 |
|---|---|---|
| committer | Mark Searles <m.c.searles@gmail.com> | 2017-06-02 14:19:25 +0000 |
| commit | 70359ac60d24bb3d68256da063219ee50bb70f01 (patch) | |
| tree | 2ba5c38eb9d690b55bdd83adc243d270ea2ac4d0 /llvm/test/CodeGen/AMDGPU/spill-m0.ll | |
| parent | 2aae0649a1ecf5b64db844d9f4b2e5ef6d45c63d (diff) | |
| download | bcm5719-llvm-70359ac60d24bb3d68256da063219ee50bb70f01.tar.gz bcm5719-llvm-70359ac60d24bb3d68256da063219ee50bb70f01.zip | |
[AMDGPU] Turn on the new waitcnt insertion pass. Adjust tests.
-enable-si-insert-waitcnts=1 becomes the default
-enable-si-insert-waitcnts=0 to use old pass
Differential Revision: https://reviews.llvm.org/D33730
llvm-svn: 304551
Diffstat (limited to 'llvm/test/CodeGen/AMDGPU/spill-m0.ll')
| -rw-r--r-- | llvm/test/CodeGen/AMDGPU/spill-m0.ll | 2 |
1 files changed, 0 insertions, 2 deletions
diff --git a/llvm/test/CodeGen/AMDGPU/spill-m0.ll b/llvm/test/CodeGen/AMDGPU/spill-m0.ll index 8f1aebfe9ce..7e8fa118c2c 100644 --- a/llvm/test/CodeGen/AMDGPU/spill-m0.ll +++ b/llvm/test/CodeGen/AMDGPU/spill-m0.ll @@ -18,13 +18,11 @@ ; TOVMEM-DAG: s_mov_b32 [[M0_COPY:s[0-9]+]], m0 ; TOVMEM-DAG: v_mov_b32_e32 [[SPILL_VREG:v[0-9]+]], [[M0_COPY]] ; TOVMEM: buffer_store_dword [[SPILL_VREG]], off, s{{\[[0-9]+:[0-9]+\]}}, s{{[0-9]+}} offset:4 ; 4-byte Folded Spill -; TOVMEM: s_waitcnt vmcnt(0) ; TOSMEM-DAG: s_mov_b32 [[M0_COPY:s[0-9]+]], m0 ; TOSMEM: s_add_u32 m0, s3, 0x100{{$}} ; TOSMEM-NOT: [[M0_COPY]] ; TOSMEM: s_buffer_store_dword [[M0_COPY]], s{{\[}}[[LO]]:[[HI]]], m0 ; 4-byte Folded Spill -; TOSMEM: s_waitcnt lgkmcnt(0) ; GCN: s_cbranch_scc1 [[ENDIF:BB[0-9]+_[0-9]+]] |
