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| author | Nicolai Haehnle <nhaehnle@gmail.com> | 2016-04-06 19:40:20 +0000 |
|---|---|---|
| committer | Nicolai Haehnle <nhaehnle@gmail.com> | 2016-04-06 19:40:20 +0000 |
| commit | df3a20cd8068c732a0b26bdf8c1857c7d97104b4 (patch) | |
| tree | 11974d0749ffa9d399f72a66fd5787d6ec248103 /llvm/test/CodeGen/AMDGPU/shared-op-cycle.ll | |
| parent | 1b6188d2f865366ef94d65b65596f47c9196c20c (diff) | |
| download | bcm5719-llvm-df3a20cd8068c732a0b26bdf8c1857c7d97104b4.tar.gz bcm5719-llvm-df3a20cd8068c732a0b26bdf8c1857c7d97104b4.zip | |
AMDGPU: Add a shader calling convention
This makes it possible to distinguish between mesa shaders
and other kernels even in the presence of compute shaders.
Patch By: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Differential Revision: http://reviews.llvm.org/D18559
llvm-svn: 265589
Diffstat (limited to 'llvm/test/CodeGen/AMDGPU/shared-op-cycle.ll')
| -rw-r--r-- | llvm/test/CodeGen/AMDGPU/shared-op-cycle.ll | 5 |
1 files changed, 2 insertions, 3 deletions
diff --git a/llvm/test/CodeGen/AMDGPU/shared-op-cycle.ll b/llvm/test/CodeGen/AMDGPU/shared-op-cycle.ll index f52a9baf4d1..8c2cbf186f5 100644 --- a/llvm/test/CodeGen/AMDGPU/shared-op-cycle.ll +++ b/llvm/test/CodeGen/AMDGPU/shared-op-cycle.ll @@ -4,7 +4,7 @@ ; CHECK: MULADD_IEEE * ; CHECK-NOT: MULADD_IEEE * -define void @main(<4 x float> inreg %reg0, <4 x float> inreg %reg1, <4 x float> inreg %reg2) #0 { +define amdgpu_vs void @main(<4 x float> inreg %reg0, <4 x float> inreg %reg1, <4 x float> inreg %reg2) { %w0 = extractelement <4 x float> %reg0, i32 3 %w1 = extractelement <4 x float> %reg1, i32 3 %w2 = extractelement <4 x float> %reg2, i32 3 @@ -28,5 +28,4 @@ declare float @llvm.AMDGPU.dp4(<4 x float>, <4 x float>) #1 declare void @llvm.R600.store.swizzle(<4 x float>, i32, i32) -attributes #0 = { "ShaderType"="1" } -attributes #1 = { readnone }
\ No newline at end of file +attributes #1 = { readnone } |
