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| author | Tom Stellard <thomas.stellard@amd.com> | 2016-11-10 16:02:37 +0000 |
|---|---|---|
| committer | Tom Stellard <thomas.stellard@amd.com> | 2016-11-10 16:02:37 +0000 |
| commit | 115a61560e24e08ecca0b3e2d16e8f1491b47f61 (patch) | |
| tree | a902f8fd2f221164e6ed9be6bbc932083293914a /llvm/test/CodeGen/AMDGPU/load-local-i16.ll | |
| parent | 2cf393c8fe6ebea1ba041de7e264f2fc7a557ab9 (diff) | |
| download | bcm5719-llvm-115a61560e24e08ecca0b3e2d16e8f1491b47f61.tar.gz bcm5719-llvm-115a61560e24e08ecca0b3e2d16e8f1491b47f61.zip | |
AMDGPU: Add VI i16 support
Patch By: Wei Ding
Differential Revision: https://reviews.llvm.org/D18049
llvm-svn: 286464
Diffstat (limited to 'llvm/test/CodeGen/AMDGPU/load-local-i16.ll')
| -rw-r--r-- | llvm/test/CodeGen/AMDGPU/load-local-i16.ll | 12 |
1 files changed, 9 insertions, 3 deletions
diff --git a/llvm/test/CodeGen/AMDGPU/load-local-i16.ll b/llvm/test/CodeGen/AMDGPU/load-local-i16.ll index 9b0cbaa7701..d4e86de66af 100644 --- a/llvm/test/CodeGen/AMDGPU/load-local-i16.ll +++ b/llvm/test/CodeGen/AMDGPU/load-local-i16.ll @@ -1,5 +1,5 @@ -; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=FUNC %s -; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=FUNC %s +; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,SI,FUNC %s +; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,VI,FUNC %s ; RUN: llc -march=r600 -mcpu=redwood < %s | FileCheck -check-prefix=EG -check-prefix=FUNC %s ; FUNC-LABEL: {{^}}local_load_i16: @@ -539,7 +539,13 @@ define void @local_zextload_i16_to_i64(i64 addrspace(3)* %out, i16 addrspace(3)* } ; FUNC-LABEL: {{^}}local_sextload_i16_to_i64: -; GCN: ds_read_i16 v[[LO:[0-9]+]], +; FIXME: Need to optimize this sequence to avoid an extra shift. +; t25: i32,ch = load<LD2[%in(addrspace=3)], anyext from i16> t12, t10, undef:i32 +; t28: i64 = any_extend t25 +; t30: i64 = sign_extend_inreg t28, ValueType:ch:i16 +; SI: ds_read_i16 v[[LO:[0-9]+]], +; VI: ds_read_u16 v[[ULO:[0-9]+]] +; VI: v_bfe_i32 v[[LO:[0-9]+]], v[[ULO]], 0, 16 ; GCN-DAG: v_ashrrev_i32_e32 v[[HI:[0-9]+]], 31, v[[LO]] ; GCN: ds_write_b64 v{{[0-9]+}}, v{{\[}}[[LO]]:[[HI]]] |
