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| author | Matthias Braun <matze@braunis.de> | 2016-05-20 23:14:56 +0000 |
|---|---|---|
| committer | Matthias Braun <matze@braunis.de> | 2016-05-20 23:14:56 +0000 |
| commit | 71f9564e7fd2ae6a0b7b8a7258591b218f51b24b (patch) | |
| tree | 005013bd54a18a6e1a35d5a344f890ee8db31cce /llvm/test/CodeGen/AMDGPU/liveness.mir | |
| parent | e29b7689bd181f35a515dac093858b56bf2a8b47 (diff) | |
| download | bcm5719-llvm-71f9564e7fd2ae6a0b7b8a7258591b218f51b24b.tar.gz bcm5719-llvm-71f9564e7fd2ae6a0b7b8a7258591b218f51b24b.zip | |
LiveIntervalAnalysis: Rework constructMainRangeFromSubranges()
We now use LiveRangeCalc::extendToUses() instead of a specially designed
algorithm in constructMainRangeFromSubranges():
- The original motivation for constructMainRangeFromSubranges() were
differences between the main liverange and subranges because of hidden
dead definitions. This case however cannot happen anymore with the
DetectDeadLaneMasks pass in place.
- It simplifies the code.
- This fixes a longstanding bug where we did not properly create new SSA
values on merging control flow (the MachineVerifier missed most of
these cases).
- Move constructMainRangeFromSubranges() to LiveIntervalAnalysis and
LiveRangeCalc to better match the implementation/available helper
functions.
This re-applies r269016. The fixes from r270290 and r270259 should avoid
the machine verifier problems this time.
llvm-svn: 270291
Diffstat (limited to 'llvm/test/CodeGen/AMDGPU/liveness.mir')
| -rw-r--r-- | llvm/test/CodeGen/AMDGPU/liveness.mir | 32 |
1 files changed, 32 insertions, 0 deletions
diff --git a/llvm/test/CodeGen/AMDGPU/liveness.mir b/llvm/test/CodeGen/AMDGPU/liveness.mir new file mode 100644 index 00000000000..ce49294d5b3 --- /dev/null +++ b/llvm/test/CodeGen/AMDGPU/liveness.mir @@ -0,0 +1,32 @@ +# RUN: llc -march=amdgcn -run-pass liveintervals -verify-machineinstrs -o /dev/null -debug-only=regalloc %s 2>&1 | FileCheck %s +# REQUIRES: asserts +# We currently maintain a main liveness range which operates like a superset of +# all subregister liveranges. We may need to create additional SSA values at +# merge point in this main liverange even though none of the subregister +# liveranges needed it. +# +# Should see three distinct value numbers: +# CHECK: %vreg0 [{{.*}}:0)[{{.*}}:1)[{{.*}}:2) 0@{{[0-9]+[Berd]}} 1@{{[0-9]+[Berd]}} 2@{{[0-9]+B-phi}} +--- | + define void @test0() { ret void } +... +--- +name: test0 +registers: + - { id: 0, class: sreg_64 } +body: | + bb.0: + successors: %bb.1, %bb.2 + S_NOP 0, implicit-def undef %0:sub0 + S_CBRANCH_VCCNZ %bb.1, implicit undef %vcc + S_BRANCH %bb.2 + + bb.1: + successors: %bb.2 + S_NOP 0, implicit-def %0:sub1 + S_NOP 0, implicit %0:sub1 + S_BRANCH %bb.2 + + bb.2: + S_NOP 0, implicit %0:sub0 +... |

