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| author | Sjoerd Meijer <sjoerd.meijer@arm.com> | 2018-02-08 08:39:05 +0000 |
|---|---|---|
| committer | Sjoerd Meijer <sjoerd.meijer@arm.com> | 2018-02-08 08:39:05 +0000 |
| commit | 5ea465ded7ef9e48a390ec60961096d8a7caf105 (patch) | |
| tree | f87a70c40af6aa0f7d5ace1671d0287fbc1324dd /llvm/test/CodeGen/AArch64 | |
| parent | 8d0c8c9be158d2c83864c3124f258f8790476602 (diff) | |
| download | bcm5719-llvm-5ea465ded7ef9e48a390ec60961096d8a7caf105.tar.gz bcm5719-llvm-5ea465ded7ef9e48a390ec60961096d8a7caf105.zip | |
[AArch64] Don't materialize 0 with "fmov h0, .." when FullFP16 is not supported
We were generating "fmov h0, wzr" instructions when FullFP16 is not enabled.
I've not added any tests, because the problem was visible in:
test/CodeGen/AArch64/arm64-zero-cycle-zeroing.ll,
which I had to change: I don't think Cyclone has FullFP16 enabled
by default, so it shouldn't be using this v8.2a instruction.
I've also removed these rdar tags, please shout if there are any objections.
Differential Revision: https://reviews.llvm.org/D43020
llvm-svn: 324581
Diffstat (limited to 'llvm/test/CodeGen/AArch64')
| -rw-r--r-- | llvm/test/CodeGen/AArch64/arm64-zero-cycle-zeroing.ll | 13 |
1 files changed, 8 insertions, 5 deletions
diff --git a/llvm/test/CodeGen/AArch64/arm64-zero-cycle-zeroing.ll b/llvm/test/CodeGen/AArch64/arm64-zero-cycle-zeroing.ll index 3acb1892dd9..664078fb7e9 100644 --- a/llvm/test/CodeGen/AArch64/arm64-zero-cycle-zeroing.ll +++ b/llvm/test/CodeGen/AArch64/arm64-zero-cycle-zeroing.ll @@ -1,12 +1,10 @@ ; RUN: llc -mtriple=arm64-apple-ios -mcpu=cyclone < %s | FileCheck %s -check-prefixes=ALL,CYCLONE +; RUN: llc -mtriple=arm64-apple-ios -mcpu=cyclone -mattr=+fullfp16 < %s | FileCheck %s -check-prefixes=CYCLONE-FULLFP16 ; RUN: llc -mtriple=aarch64-gnu-linux -mcpu=exynos-m1 < %s | FileCheck %s -check-prefixes=ALL,OTHERS ; RUN: llc -mtriple=aarch64-gnu-linux -mcpu=exynos-m3 < %s | FileCheck %s -check-prefixes=ALL,OTHERS ; RUN: llc -mtriple=aarch64-gnu-linux -mcpu=kryo < %s | FileCheck %s -check-prefixes=ALL,OTHERS ; RUN: llc -mtriple=aarch64-gnu-linux -mcpu=falkor < %s | FileCheck %s -check-prefixes=ALL,OTHERS -; rdar://11481771 -; rdar://13713797 - declare void @bar(half, float, double, <2 x double>) declare void @bari(i32, i32) declare void @barl(i64, i64) @@ -16,11 +14,14 @@ define void @t1() nounwind ssp { entry: ; ALL-LABEL: t1: ; ALL-NOT: fmov -; CYCLONE: fmov h0, wzr +; ALL: ldr h0,{{.*}} ; CYCLONE: fmov s1, wzr ; CYCLONE: fmov d2, xzr ; CYCLONE: movi.16b v3, #0 -; OTHERS: movi v{{[0-3]+}}.2d, #0000000000000000 +; CYCLONE-FULLFP16: fmov h0, wzr +; CYCLONE-FULLFP16: fmov s1, wzr +; CYCLONE-FULLFP16: fmov d2, xzr +; CYCLONE-FULLFP16: movi.16b v3, #0 ; OTHERS: movi v{{[0-3]+}}.2d, #0000000000000000 ; OTHERS: movi v{{[0-3]+}}.2d, #0000000000000000 ; OTHERS: movi v{{[0-3]+}}.2d, #0000000000000000 @@ -53,6 +54,8 @@ define void @t4() nounwind ssp { ; ALL-NOT: fmov ; CYCLONE: fmov s{{[0-3]+}}, wzr ; CYCLONE: fmov s{{[0-3]+}}, wzr +; CYCLONE-FULLFP16: fmov s{{[0-3]+}}, wzr +; CYCLONE-FULLFP16: fmov s{{[0-3]+}}, wzr ; OTHERS: movi v{{[0-3]+}}.2d, #0000000000000000 ; OTHERS: movi v{{[0-3]+}}.2d, #0000000000000000 tail call void @barf(float 0.000000e+00, float 0.000000e+00) nounwind |
