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| author | Tim Northover <tnorthover@apple.com> | 2014-05-15 11:16:32 +0000 |
|---|---|---|
| committer | Tim Northover <tnorthover@apple.com> | 2014-05-15 11:16:32 +0000 |
| commit | d8d65a69cfb608724e071048350b9616228dfe34 (patch) | |
| tree | 009f769115178cfbebd034aa7481523152978316 /llvm/test/CodeGen/AArch64/neon-copyPhysReg-tuple.ll | |
| parent | dd8fca513682f6899d36b7161e48659fa216bba2 (diff) | |
| download | bcm5719-llvm-d8d65a69cfb608724e071048350b9616228dfe34.tar.gz bcm5719-llvm-d8d65a69cfb608724e071048350b9616228dfe34.zip | |
TableGen/ARM64: print aliases even if they have syntax variants.
To get at least one use of the change (and some actual tests) in with its
commit, I've enabled the AArch64 & ARM64 NEON mov aliases.
llvm-svn: 208867
Diffstat (limited to 'llvm/test/CodeGen/AArch64/neon-copyPhysReg-tuple.ll')
| -rw-r--r-- | llvm/test/CodeGen/AArch64/neon-copyPhysReg-tuple.ll | 18 |
1 files changed, 9 insertions, 9 deletions
diff --git a/llvm/test/CodeGen/AArch64/neon-copyPhysReg-tuple.ll b/llvm/test/CodeGen/AArch64/neon-copyPhysReg-tuple.ll index 186a76909ec..1256b2b6504 100644 --- a/llvm/test/CodeGen/AArch64/neon-copyPhysReg-tuple.ll +++ b/llvm/test/CodeGen/AArch64/neon-copyPhysReg-tuple.ll @@ -3,8 +3,8 @@ define <4 x i32> @copyTuple.QPair(i8* %a, i8* %b) { ; CHECK-LABEL: copyTuple.QPair: -; CHECK: orr v{{[0-9]+}}.16b, v{{[0-9]+}}.16b, v{{[0-9]+}}.16b -; CHECK: orr v{{[0-9]+}}.16b, v{{[0-9]+}}.16b, v{{[0-9]+}}.16b +; CHECK: mov v{{[0-9]+}}.16b, v{{[0-9]+}}.16b +; CHECK: mov v{{[0-9]+}}.16b, v{{[0-9]+}}.16b ; CHECK: ld2 { {{v[0-9]+}}.s, {{v[0-9]+}}.s }[{{[0-9]+}}], [x{{[0-9]+|sp}}] entry: %vld = tail call { <4 x i32>, <4 x i32> } @llvm.arm.neon.vld2lane.v4i32(i8* %a, <4 x i32> <i32 -1, i32 -1, i32 -1, i32 -1>, <4 x i32> <i32 2, i32 2, i32 2, i32 2>, i32 0, i32 4) @@ -16,9 +16,9 @@ entry: define <4 x i32> @copyTuple.QTriple(i8* %a, i8* %b, <4 x i32> %c) { ; CHECK-LABEL: copyTuple.QTriple: -; CHECK: orr v{{[0-9]+}}.16b, v{{[0-9]+}}.16b, v{{[0-9]+}}.16b -; CHECK: orr v{{[0-9]+}}.16b, v{{[0-9]+}}.16b, v{{[0-9]+}}.16b -; CHECK: orr v{{[0-9]+}}.16b, v{{[0-9]+}}.16b, v{{[0-9]+}}.16b +; CHECK: mov v{{[0-9]+}}.16b, v{{[0-9]+}}.16b +; CHECK: mov v{{[0-9]+}}.16b, v{{[0-9]+}}.16b +; CHECK: mov v{{[0-9]+}}.16b, v{{[0-9]+}}.16b ; CHECK: ld3 { {{v[0-9]+}}.s, {{v[0-9]+}}.s, {{v[0-9]+}}.s }[{{[0-9]+}}], [x{{[0-9]+|sp}}] entry: %vld = tail call { <4 x i32>, <4 x i32>, <4 x i32> } @llvm.arm.neon.vld3lane.v4i32(i8* %a, <4 x i32> <i32 -1, i32 -1, i32 -1, i32 -1>, <4 x i32> %c, <4 x i32> %c, i32 0, i32 4) @@ -30,10 +30,10 @@ entry: define <4 x i32> @copyTuple.QQuad(i8* %a, i8* %b, <4 x i32> %c) { ; CHECK-LABEL: copyTuple.QQuad: -; CHECK: orr v{{[0-9]+}}.16b, v{{[0-9]+}}.16b, v{{[0-9]+}}.16b -; CHECK: orr v{{[0-9]+}}.16b, v{{[0-9]+}}.16b, v{{[0-9]+}}.16b -; CHECK: orr v{{[0-9]+}}.16b, v{{[0-9]+}}.16b, v{{[0-9]+}}.16b -; CHECK: orr v{{[0-9]+}}.16b, v{{[0-9]+}}.16b, v{{[0-9]+}}.16b +; CHECK: mov v{{[0-9]+}}.16b, v{{[0-9]+}}.16b +; CHECK: mov v{{[0-9]+}}.16b, v{{[0-9]+}}.16b +; CHECK: mov v{{[0-9]+}}.16b, v{{[0-9]+}}.16b +; CHECK: mov v{{[0-9]+}}.16b, v{{[0-9]+}}.16b ; CHECK: ld4 { {{v[0-9]+}}.s, {{v[0-9]+}}.s, {{v[0-9]+}}.s, {{v[0-9]+}}.s }[{{[0-9]+}}], [x{{[0-9]+|sp}}] entry: %vld = tail call { <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32> } @llvm.arm.neon.vld4lane.v4i32(i8* %a, <4 x i32> <i32 -1, i32 -1, i32 -1, i32 -1>, <4 x i32> %c, <4 x i32> %c, <4 x i32> %c, i32 0, i32 4) |
