[opaque pointer type] Add textual IR support for explicit type parameter to load instruction

Essentially the same as the GEP change in r230786.

A similar migration script can be used to update test cases, though a few more
test case improvements/changes were required this time around: (r229269-r229278)

import fileinput
import sys
import re

pat = re.compile(r"((?:=|:|^)\s*load (?:atomic )?(?:volatile )?(.*?))(| addrspace\(\d+\) *)\*($| *(?:%|@|null|undef|blockaddress|getelementptr|addrspacecast|bitcast|inttoptr|\[\[[a-zA-Z]|\{\{).*$)")

for line in sys.stdin:
  sys.stdout.write(re.sub(pat, r"\1, \2\3*\4", line))

Reviewers: rafael, dexonsmith, grosser

Differential Revision: http://reviews.llvm.org/D7649

llvm-svn: 230794

1 files changed, 10 insertions, 10 deletions

diff --git a/llvm/test/CodeGen/AArch64/fast-isel-int-ext3.ll b/llvm/test/CodeGen/AArch64/fast-isel-int-ext3.ll
index 5d55a6b38f6..83740c8af5f 100644
--- a/llvm/test/CodeGen/AArch64/fast-isel-int-ext3.ll
+++ b/llvm/test/CodeGen/AArch64/fast-isel-int-ext3.ll
@@ -11,7 +11,7 @@ define i32 @load_unscaled_zext_i8_to_i32(i64 %a) {
 ; CHECK:       uxtb w0, [[REG]]
   %1 = sub i64 %a, 8
   %2 = inttoptr i64 %1 to i8 addrspace(256)*
-  %3 = load i8 addrspace(256)* %2
+  %3 = load i8, i8 addrspace(256)* %2
   %4 = zext i8 %3 to i32
   ret i32 %4
 }
@@ -22,7 +22,7 @@ define i32 @load_unscaled_zext_i16_to_i32(i64 %a) {
 ; CHECK:       uxth w0, [[REG]]
   %1 = sub i64 %a, 8
   %2 = inttoptr i64 %1 to i16 addrspace(256)*
-  %3 = load i16 addrspace(256)* %2
+  %3 = load i16, i16 addrspace(256)* %2
   %4 = zext i16 %3 to i32
   ret i32 %4
 }
@@ -33,7 +33,7 @@ define i64 @load_unscaled_zext_i8_to_i64(i64 %a) {
 ; CHECK:       ubfx x0, x[[REG]], #0, #8
   %1 = sub i64 %a, 8
   %2 = inttoptr i64 %1 to i8 addrspace(256)*
-  %3 = load i8 addrspace(256)* %2
+  %3 = load i8, i8 addrspace(256)* %2
   %4 = zext i8 %3 to i64
   ret i64 %4
 }
@@ -44,7 +44,7 @@ define i64 @load_unscaled_zext_i16_to_i64(i64 %a) {
 ; CHECK:       ubfx x0, x[[REG]], #0, #16
   %1 = sub i64 %a, 8
   %2 = inttoptr i64 %1 to i16 addrspace(256)*
-  %3 = load i16 addrspace(256)* %2
+  %3 = load i16, i16 addrspace(256)* %2
   %4 = zext i16 %3 to i64
   ret i64 %4
 }
@@ -55,7 +55,7 @@ define i64 @load_unscaled_zext_i32_to_i64(i64 %a) {
 ; CHECK:       ubfx x0, x[[REG]], #0, #32
   %1 = sub i64 %a, 8
   %2 = inttoptr i64 %1 to i32 addrspace(256)*
-  %3 = load i32 addrspace(256)* %2
+  %3 = load i32, i32 addrspace(256)* %2
   %4 = zext i32 %3 to i64
   ret i64 %4
 }
@@ -66,7 +66,7 @@ define i32 @load_unscaled_sext_i8_to_i32(i64 %a) {
 ; CHECK:       sxtb w0, [[REG]]
   %1 = sub i64 %a, 8
   %2 = inttoptr i64 %1 to i8 addrspace(256)*
-  %3 = load i8 addrspace(256)* %2
+  %3 = load i8, i8 addrspace(256)* %2
   %4 = sext i8 %3 to i32
   ret i32 %4
 }
@@ -77,7 +77,7 @@ define i32 @load_unscaled_sext_i16_to_i32(i64 %a) {
 ; CHECK:       sxth w0, [[REG]]
   %1 = sub i64 %a, 8
   %2 = inttoptr i64 %1 to i16 addrspace(256)*
-  %3 = load i16 addrspace(256)* %2
+  %3 = load i16, i16 addrspace(256)* %2
   %4 = sext i16 %3 to i32
   ret i32 %4
 }
@@ -88,7 +88,7 @@ define i64 @load_unscaled_sext_i8_to_i64(i64 %a) {
 ; CHECK:       sxtb x0, [[REG]]
   %1 = sub i64 %a, 8
   %2 = inttoptr i64 %1 to i8 addrspace(256)*
-  %3 = load i8 addrspace(256)* %2
+  %3 = load i8, i8 addrspace(256)* %2
   %4 = sext i8 %3 to i64
   ret i64 %4
 }
@@ -99,7 +99,7 @@ define i64 @load_unscaled_sext_i16_to_i64(i64 %a) {
 ; CHECK:       sxth x0, [[REG]]
   %1 = sub i64 %a, 8
   %2 = inttoptr i64 %1 to i16 addrspace(256)*
-  %3 = load i16 addrspace(256)* %2
+  %3 = load i16, i16 addrspace(256)* %2
   %4 = sext i16 %3 to i64
   ret i64 %4
 }
@@ -110,7 +110,7 @@ define i64 @load_unscaled_sext_i32_to_i64(i64 %a) {
 ; CHECK:       sxtw x0, [[REG]]
   %1 = sub i64 %a, 8
   %2 = inttoptr i64 %1 to i32 addrspace(256)*
-  %3 = load i32 addrspace(256)* %2
+  %3 = load i32, i32 addrspace(256)* %2
   %4 = sext i32 %3 to i64
   ret i64 %4
 }