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| author | Craig Topper <craig.topper@intel.com> | 2018-03-20 03:01:59 +0000 |
|---|---|---|
| committer | Craig Topper <craig.topper@intel.com> | 2018-03-20 03:01:59 +0000 |
| commit | 7c90e29cf8f46d4c4de772e1e64d2620b2bbaf23 (patch) | |
| tree | 67f7950dc0457b1dea7a642e0136707aefb188eb /llvm/test/Bitcode/thinlto-function-summary-functionattrs.ll | |
| parent | 508f68233d060987951ab1699ca9cf03110e92b0 (diff) | |
| download | bcm5719-llvm-7c90e29cf8f46d4c4de772e1e64d2620b2bbaf23.tar.gz bcm5719-llvm-7c90e29cf8f46d4c4de772e1e64d2620b2bbaf23.zip | |
[X86] Add ROR/ROL/SHR/SAR by 1 instructions to the Sandy Bridge scheduler model.
I assume these match the generic immediate version like they do in the other models.
llvm-svn: 327943
Diffstat (limited to 'llvm/test/Bitcode/thinlto-function-summary-functionattrs.ll')
0 files changed, 0 insertions, 0 deletions
