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| author | dfukalov <daniil.fukalov@amd.com> | 2019-11-06 22:05:58 +0300 |
|---|---|---|
| committer | dfukalov <daniil.fukalov@amd.com> | 2019-11-07 11:50:14 +0300 |
| commit | 6e8251046b96ae9b1ab8fc0f864266222856b5c5 (patch) | |
| tree | aff25d81b158d69f11317bf23bbdad6b6ca66df6 /llvm/test/Analysis/CostModel | |
| parent | 96065cf79ff76d5fd4fdaeb2fb2650074b3e0e51 (diff) | |
| download | bcm5719-llvm-6e8251046b96ae9b1ab8fc0f864266222856b5c5.tar.gz bcm5719-llvm-6e8251046b96ae9b1ab8fc0f864266222856b5c5.zip | |
[AMDGPU] Fix bug introduced in 47a5c36b37f0
Summary: [AMDGPU] Fix bug introduced in 47a5c36b37f0
Reviewers: foad, arsenm
Reviewed By: arsenm
Subscribers: arsenm, kzhuravl, jvesely, wdng, nhaehnle, yaxunl, dstuttard, tpr, t-tye, hiraditya, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D69915
Diffstat (limited to 'llvm/test/Analysis/CostModel')
| -rw-r--r-- | llvm/test/Analysis/CostModel/AMDGPU/shufflevector.ll | 19 |
1 files changed, 15 insertions, 4 deletions
diff --git a/llvm/test/Analysis/CostModel/AMDGPU/shufflevector.ll b/llvm/test/Analysis/CostModel/AMDGPU/shufflevector.ll index 413dd5ea2a8..ff3abcaab46 100644 --- a/llvm/test/Analysis/CostModel/AMDGPU/shufflevector.ll +++ b/llvm/test/Analysis/CostModel/AMDGPU/shufflevector.ll @@ -1,7 +1,7 @@ -; RUN: opt -cost-model -analyze -mtriple=amdgcn-unknown-amdhsa -mcpu=gfx900 %s | FileCheck -check-prefixes=GFX9,GCN %s -; RUN: opt -cost-model -analyze -mtriple=amdgcn-unknown-amdhsa -mcpu=fiji %s | FileCheck -check-prefixes=VI,GCN %s -; RUN: opt -cost-model -cost-kind=code-size -analyze -mtriple=amdgcn-unknown-amdhsa -mcpu=gfx900 %s | FileCheck -check-prefixes=GFX9,GCN %s -; RUN: opt -cost-model -cost-kind=code-size -analyze -mtriple=amdgcn-unknown-amdhsa -mcpu=fiji %s | FileCheck -check-prefixes=VI,GCN %s +; RUN: opt -cost-model -analyze -mtriple=amdgcn-unknown-amdhsa -mcpu=gfx900 %s | FileCheck -check-prefixes=GFX9,GCN,TPT %s +; RUN: opt -cost-model -analyze -mtriple=amdgcn-unknown-amdhsa -mcpu=fiji %s | FileCheck -check-prefixes=VI,GCN,TPT %s +; RUN: opt -cost-model -cost-kind=code-size -analyze -mtriple=amdgcn-unknown-amdhsa -mcpu=gfx900 %s | FileCheck -check-prefixes=GFX9,GCN,CS %s +; RUN: opt -cost-model -cost-kind=code-size -analyze -mtriple=amdgcn-unknown-amdhsa -mcpu=fiji %s | FileCheck -check-prefixes=VI,GCN,CS %s ; GCN-LABEL: 'shufflevector_00_v2i16' ; GFX9: estimated cost of 0 for {{.*}} shufflevector <2 x i16> %vec, <2 x i16> undef, <2 x i32> zeroinitializer @@ -51,3 +51,14 @@ define amdgpu_kernel void @shufflevector_02_v2i16(<2 x i16> addrspace(1)* %out, store <2 x i16> %shuf, <2 x i16> addrspace(1)* %out ret void } + +; GCN-LABEL: 'shufflevector_xxx' +; TPT: Unknown cost for {{.*}} shufflevector <2 x i8> %vec, <2 x i8> undef, <4 x i32> <i32 0, i32 1, i32 undef, i32 undef> +; CS: estimated cost of 1 for {{.*}} shufflevector <2 x i8> %vec, <2 x i8> undef, <4 x i32> <i32 0, i32 1, i32 undef, i32 undef> +; Should not assert +define amdgpu_kernel void @shufflevector_xxx(<4 x i8> addrspace(1)* %out, <2 x i8> addrspace(1)* %vaddr) { + %vec = load <2 x i8>, <2 x i8> addrspace(1)* %vaddr + %shuf = shufflevector <2 x i8> %vec, <2 x i8> undef, <4 x i32> <i32 0, i32 1, i32 undef, i32 undef> + store <4 x i8> %shuf, <4 x i8> addrspace(1)* %out + ret void +} |
