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| author | Nate Begeman <natebegeman@mac.com> | 2005-04-03 22:13:27 +0000 |
|---|---|---|
| committer | Nate Begeman <natebegeman@mac.com> | 2005-04-03 22:13:27 +0000 |
| commit | f6dc43bd46b774040d19e368394ac04d276702fe (patch) | |
| tree | 645c5a9b4346dfb6fdd0cb1b613adcf5ef54b362 /llvm/lib | |
| parent | 79e727e8a7fdedb2a1311d5fb0e41ec6e81d306b (diff) | |
| download | bcm5719-llvm-f6dc43bd46b774040d19e368394ac04d276702fe.tar.gz bcm5719-llvm-f6dc43bd46b774040d19e368394ac04d276702fe.zip | |
Fix SHL_PARTS
Start implementation of integer varargs
llvm-svn: 21065
Diffstat (limited to 'llvm/lib')
| -rw-r--r-- | llvm/lib/Target/PowerPC/PPC32ISelPattern.cpp | 12 |
1 files changed, 10 insertions, 2 deletions
diff --git a/llvm/lib/Target/PowerPC/PPC32ISelPattern.cpp b/llvm/lib/Target/PowerPC/PPC32ISelPattern.cpp index 88ad79dbc8e..6c6ad337b94 100644 --- a/llvm/lib/Target/PowerPC/PPC32ISelPattern.cpp +++ b/llvm/lib/Target/PowerPC/PPC32ISelPattern.cpp @@ -192,8 +192,16 @@ PPC32TargetLowering::LowerArguments(Function &F, SelectionDAG &DAG) { // If the function takes variable number of arguments, make a frame index for // the start of the first vararg value... for expansion of llvm.va_start. - if (F.isVarArg()) + if (F.isVarArg()) { VarArgsFrameIndex = MFI->CreateFixedObject(4, ArgOffset); + // If this function is vararg, store r4-r10 to their spots on the stack so + // that they may be loaded by dereferencing va_next + SDOperand FIN = DAG.getFrameIndex(VarArgsFrameIndex, MVT::i32); + SDOperand Val = DAG.getCopyFromReg(PPC::R4, MVT::i32, DAG.getRoot()); + SDOperand Store = DAG.getNode(ISD::STORE, MVT::Other, Val, Val, FIN); + DAG.setRoot(Val.getValue(1)); + ArgValues.push_back(Store); + } return ArgValues; } @@ -1352,7 +1360,7 @@ unsigned ISel::SelectExpr(SDOperand N) { BuildMI(BB, PPC::SRW, 2, Tmp3).addReg(ShiftOpLo).addReg(Tmp1); BuildMI(BB, PPC::OR, 2, Tmp4).addReg(Tmp2).addReg(Tmp3); BuildMI(BB, PPC::ADDI, 2, Tmp5).addReg(SHReg).addSImm(-32); - BuildMI(BB, PPC::SLW, 2, Tmp6).addReg(ShiftOpHi).addReg(Tmp5); + BuildMI(BB, PPC::SLW, 2, Tmp6).addReg(ShiftOpLo).addReg(Tmp5); BuildMI(BB, PPC::OR, 2, Result+1).addReg(Tmp4).addReg(Tmp6); BuildMI(BB, PPC::SLW, 2, Result).addReg(ShiftOpLo).addReg(SHReg); } else if (ISD::SRL_PARTS == opcode) { |
