support for Schedule included on Mips.td

llvm-svn: 41159

2 files changed, 15 insertions, 28 deletions

diff --git a/llvm/lib/Target/Mips/Mips.td b/llvm/lib/Target/Mips/Mips.td
index 662bc3b85d8..8beb3fb8953 100644
--- a/llvm/lib/Target/Mips/Mips.td
+++ b/llvm/lib/Target/Mips/Mips.td
@@ -6,58 +6,44 @@
 // University of Illinois Open Source License. See LICENSE.TXT for details.
 //
 //===----------------------------------------------------------------------===//
+// This is the top level entry point for the Mips target.
+//===----------------------------------------------------------------------===//
 
 //===----------------------------------------------------------------------===//
-// Target-independent interfaces which we are implementing
+// Target-independent interfaces
 //===----------------------------------------------------------------------===//
 
 include "../Target.td"
 
 //===----------------------------------------------------------------------===//
-// Register File Description
+// Descriptions
 //===----------------------------------------------------------------------===//
 
 include "MipsRegisterInfo.td"
-
-//===----------------------------------------------------------------------===//
-// Subtarget features
-//===----------------------------------------------------------------------===//
-
-// TODO: dummy, needed to compile
-def FeatureCIX : SubtargetFeature<"r3000", "isR3000", "true",
-                                  "Enable r3000 extentions">;
-
-//===----------------------------------------------------------------------===//
-// Instruction Description
-//===----------------------------------------------------------------------===//
-
+include "MipsSchedule.td"
 include "MipsInstrInfo.td"
+include "MipsCallingConv.td"
 
 def MipsInstrInfo : InstrInfo {
-  // Define how we want to layout our target-specific information field.
   let TSFlagsFields = [];
   let TSFlagsShifts = [];
 }
+
 //===----------------------------------------------------------------------===//
-// Calling Conventions
+// CPU Directives                                                             //
 //===----------------------------------------------------------------------===//
 
-include "MipsCallingConv.td"
+def FeatureMipsIII : SubtargetFeature<"mips3", "IsMipsIII", "true",
+                                      "MipsIII ISA Support">;
 
 //===----------------------------------------------------------------------===//
 // Mips processors supported.
 //===----------------------------------------------------------------------===//
 
-class Proc<string Name, list<SubtargetFeature> Features>
- : Processor<Name, NoItineraries, Features>;
-
-def : Proc<"generic", []>;
-
-//===----------------------------------------------------------------------===//
-// Declare the target which we are implementing
-//===----------------------------------------------------------------------===//
+def : Processor<"generic", MipsGenericItineraries, []>;
+//def : Processor<"r4000",   MipsR4000Itineraries,   [FeatureMipsIII]>;
 
 def Mips : Target {
-  // Pull in Instruction Info:
   let InstructionSet = MipsInstrInfo;
 }
+
diff --git a/llvm/lib/Target/Mips/MipsSubtarget.cpp b/llvm/lib/Target/Mips/MipsSubtarget.cpp
index a394f774ab8..4665279df69 100644
--- a/llvm/lib/Target/Mips/MipsSubtarget.cpp
+++ b/llvm/lib/Target/Mips/MipsSubtarget.cpp
@@ -17,7 +17,8 @@
 using namespace llvm;
 
 MipsSubtarget::MipsSubtarget(const TargetMachine &TM, const Module &M, 
-                             const std::string &FS) : isR3000(false) 
+                             const std::string &FS) : 
+  IsMipsIII(false)
 {
   std::string CPU = "generic";