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| author | Chad Rosier <mcrosier@codeaurora.org> | 2014-08-25 16:56:33 +0000 |
|---|---|---|
| committer | Chad Rosier <mcrosier@codeaurora.org> | 2014-08-25 16:56:33 +0000 |
| commit | e62f365458e5621599908152840818a55cabd382 (patch) | |
| tree | f9b34a33a50043e9889a843982831a468bb41dcc /llvm/lib | |
| parent | dc8caada51697237ff2d83dbf237c2ad51a83234 (diff) | |
| download | bcm5719-llvm-e62f365458e5621599908152840818a55cabd382.tar.gz bcm5719-llvm-e62f365458e5621599908152840818a55cabd382.zip | |
[AArch32] Add patterns for VCVT{A,N,P,M}.
Patterns for lowering libm calls to VCVT{A,N,P,M} are also included.
Phabricator Revision: http://reviews.llvm.org/D5033
llvm-svn: 216388
Diffstat (limited to 'llvm/lib')
| -rw-r--r-- | llvm/lib/Target/ARM/ARMInstrVFP.td | 22 |
1 files changed, 13 insertions, 9 deletions
diff --git a/llvm/lib/Target/ARM/ARMInstrVFP.td b/llvm/lib/Target/ARM/ARMInstrVFP.td index 90223213a2e..d78f2ac8e21 100644 --- a/llvm/lib/Target/ARM/ARMInstrVFP.td +++ b/llvm/lib/Target/ARM/ARMInstrVFP.td @@ -627,27 +627,30 @@ def : Pat<(f16_to_fp GPR:$a), def : Pat<(f64 (f16_to_fp GPR:$a)), (VCVTBHD (COPY_TO_REGCLASS GPR:$a, SPR))>; - -multiclass vcvt_inst<string opc, bits<2> rm> { +multiclass vcvt_inst<string opc, bits<2> rm, + SDPatternOperator node = null_frag> { let PostEncoderMethod = "", DecoderNamespace = "VFPV8" in { def SS : ASuInp<0b11101, 0b11, 0b1100, 0b11, 0, (outs SPR:$Sd), (ins SPR:$Sm), NoItinerary, !strconcat("vcvt", opc, ".s32.f32\t$Sd, $Sm"), - []>, Requires<[HasFPARMv8]> { + [(set SPR:$Sd, (arm_ftosi (node SPR:$Sm)))]>, + Requires<[HasFPARMv8]> { let Inst{17-16} = rm; } def US : ASuInp<0b11101, 0b11, 0b1100, 0b01, 0, (outs SPR:$Sd), (ins SPR:$Sm), NoItinerary, !strconcat("vcvt", opc, ".u32.f32\t$Sd, $Sm"), - []>, Requires<[HasFPARMv8]> { + [(set SPR:$Sd, (arm_ftoui (node SPR:$Sm)))]>, + Requires<[HasFPARMv8]> { let Inst{17-16} = rm; } def SD : ASuInp<0b11101, 0b11, 0b1100, 0b11, 0, (outs SPR:$Sd), (ins DPR:$Dm), NoItinerary, !strconcat("vcvt", opc, ".s32.f64\t$Sd, $Dm"), - []>, Requires<[HasFPARMv8, HasDPVFP]> { + [(set SPR:$Sd, (arm_ftosi (f64 (node (f64 DPR:$Dm)))))]>, + Requires<[HasFPARMv8, HasDPVFP]> { bits<5> Dm; let Inst{17-16} = rm; @@ -661,7 +664,8 @@ multiclass vcvt_inst<string opc, bits<2> rm> { def UD : ASuInp<0b11101, 0b11, 0b1100, 0b01, 0, (outs SPR:$Sd), (ins DPR:$Dm), NoItinerary, !strconcat("vcvt", opc, ".u32.f64\t$Sd, $Dm"), - []>, Requires<[HasFPARMv8, HasDPVFP]> { + [(set SPR:$Sd, (arm_ftoui (f64 (node (f64 DPR:$Dm)))))]>, + Requires<[HasFPARMv8, HasDPVFP]> { bits<5> Dm; let Inst{17-16} = rm; @@ -674,10 +678,10 @@ multiclass vcvt_inst<string opc, bits<2> rm> { } } -defm VCVTA : vcvt_inst<"a", 0b00>; +defm VCVTA : vcvt_inst<"a", 0b00, frnd>; defm VCVTN : vcvt_inst<"n", 0b01>; -defm VCVTP : vcvt_inst<"p", 0b10>; -defm VCVTM : vcvt_inst<"m", 0b11>; +defm VCVTP : vcvt_inst<"p", 0b10, fceil>; +defm VCVTM : vcvt_inst<"m", 0b11, ffloor>; def VNEGD : ADuI<0b11101, 0b11, 0b0001, 0b01, 0, (outs DPR:$Dd), (ins DPR:$Dm), |
