diff options
| author | Jim Grosbach <grosbach@apple.com> | 2010-11-11 20:05:40 +0000 |
|---|---|---|
| committer | Jim Grosbach <grosbach@apple.com> | 2010-11-11 20:05:40 +0000 |
| commit | c33f28bf90d42824de226b76ffde33e706d42c33 (patch) | |
| tree | 4c6605f46608629a0e2348bd586d010c62863c8e /llvm/lib | |
| parent | b90f7004cff7329b35e642a7066b800640fde48f (diff) | |
| download | bcm5719-llvm-c33f28bf90d42824de226b76ffde33e706d42c33.tar.gz bcm5719-llvm-c33f28bf90d42824de226b76ffde33e706d42c33.zip | |
ARM fixup encoding for direct call instructions (BL).
llvm-svn: 118829
Diffstat (limited to 'llvm/lib')
| -rw-r--r-- | llvm/lib/Target/ARM/ARMInstrInfo.td | 30 |
1 files changed, 22 insertions, 8 deletions
diff --git a/llvm/lib/Target/ARM/ARMInstrInfo.td b/llvm/lib/Target/ARM/ARMInstrInfo.td index 3465e9879e4..b8948322c20 100644 --- a/llvm/lib/Target/ARM/ARMInstrInfo.td +++ b/llvm/lib/Target/ARM/ARMInstrInfo.td @@ -278,6 +278,12 @@ def brtarget : Operand<OtherVT> { string EncoderMethod = "getBranchTargetOpValue"; } +// Call target. +def bltarget : Operand<i32> { + // Encoded the same as branch targets. + string EncoderMethod = "getBranchTargetOpValue"; +} + // A list of registers separated by comma. Used by load/store multiple. def reglist : Operand<i32> { string EncoderMethod = "getRegisterListOpValue"; @@ -1198,18 +1204,22 @@ let isCall = 1, D0, D1, D2, D3, D4, D5, D6, D7, D16, D17, D18, D19, D20, D21, D22, D23, D24, D25, D26, D27, D28, D29, D30, D31, CPSR, FPSCR] in { - def BL : ABXI<0b1011, (outs), (ins i32imm:$func, variable_ops), + def BL : ABXI<0b1011, (outs), (ins bltarget:$func, variable_ops), IIC_Br, "bl\t$func", [(ARMcall tglobaladdr:$func)]>, Requires<[IsARM, IsNotDarwin]> { let Inst{31-28} = 0b1110; - // FIXME: Encoding info for $func. Needs fixups bits. + bits<24> func; + let Inst{23-0} = func; } - def BL_pred : ABI<0b1011, (outs), (ins i32imm:$func, variable_ops), + def BL_pred : ABI<0b1011, (outs), (ins bltarget:$func, variable_ops), IIC_Br, "bl", "\t$func", [(ARMcall_pred tglobaladdr:$func)]>, - Requires<[IsARM, IsNotDarwin]>; + Requires<[IsARM, IsNotDarwin]> { + bits<24> func; + let Inst{23-0} = func; + } // ARMv5T and above def BLX : AXI<(outs), (ins GPR:$func, variable_ops), BrMiscFrm, @@ -1249,17 +1259,21 @@ let isCall = 1, D0, D1, D2, D3, D4, D5, D6, D7, D16, D17, D18, D19, D20, D21, D22, D23, D24, D25, D26, D27, D28, D29, D30, D31, CPSR, FPSCR] in { - def BLr9 : ABXI<0b1011, (outs), (ins i32imm:$func, variable_ops), + def BLr9 : ABXI<0b1011, (outs), (ins bltarget:$func, variable_ops), IIC_Br, "bl\t$func", [(ARMcall tglobaladdr:$func)]>, Requires<[IsARM, IsDarwin]> { let Inst{31-28} = 0b1110; - // FIXME: Encoding info for $func. Needs fixups bits. + bits<24> func; + let Inst{23-0} = func; } - def BLr9_pred : ABI<0b1011, (outs), (ins i32imm:$func, variable_ops), + def BLr9_pred : ABI<0b1011, (outs), (ins bltarget:$func, variable_ops), IIC_Br, "bl", "\t$func", [(ARMcall_pred tglobaladdr:$func)]>, - Requires<[IsARM, IsDarwin]>; + Requires<[IsARM, IsDarwin]> { + bits<24> func; + let Inst{23-0} = func; + } // ARMv5T and above def BLXr9 : AXI<(outs), (ins GPR:$func, variable_ops), BrMiscFrm, |
