[codeview] Use push_macro to avoid conflicts instead of a prefix

Summary:
This prefix was added in r333421, and it changed our dumper output to
say things like "CVRegEAX" instead of just "EAX". That's a functional
change that I'd rather avoid.

I tested GCC, Clang, and MSVC, and all of them support #pragma
push_macro. They don't issue warnings whem the macro is not defined
either.

I don't have a Mac so I can't test the real termios.h header, but I
looked at the termios.h sources online and looked for other conflicts.
I saw only the CR* macros, so those are the ones we work around.

Reviewers: zturner, JDevlieghere

Subscribers: hiraditya, llvm-commits

Differential Revision: https://reviews.llvm.org/D50851

llvm-svn: 339907

2 files changed, 172 insertions, 172 deletions

diff --git a/llvm/lib/DebugInfo/PDB/Native/NativeRawSymbol.cpp b/llvm/lib/DebugInfo/PDB/Native/NativeRawSymbol.cpp
index a4b02959631..fbe334823e0 100644
--- a/llvm/lib/DebugInfo/PDB/Native/NativeRawSymbol.cpp
+++ b/llvm/lib/DebugInfo/PDB/Native/NativeRawSymbol.cpp
@@ -188,7 +188,7 @@ uint32_t NativeRawSymbol::getLiveRangeStartRelativeVirtualAddress() const {
 }
 
 codeview::RegisterId NativeRawSymbol::getLocalBasePointerRegisterId() const {
-  return codeview::RegisterId::CVRegEAX;
+  return codeview::RegisterId::EAX;
 }
 
 uint32_t NativeRawSymbol::getLowerBoundId() const {
@@ -248,7 +248,7 @@ uint32_t NativeRawSymbol::getRank() const {
 }
 
 codeview::RegisterId NativeRawSymbol::getRegisterId() const {
-  return codeview::RegisterId::CVRegEAX;
+  return codeview::RegisterId::EAX;
 }
 
 uint32_t NativeRawSymbol::getRegisterType() const {
diff --git a/llvm/lib/Target/X86/MCTargetDesc/X86MCTargetDesc.cpp b/llvm/lib/Target/X86/MCTargetDesc/X86MCTargetDesc.cpp
index 99590c5de8c..355b90b5459 100644
--- a/llvm/lib/Target/X86/MCTargetDesc/X86MCTargetDesc.cpp
+++ b/llvm/lib/Target/X86/MCTargetDesc/X86MCTargetDesc.cpp
@@ -81,176 +81,176 @@ void X86_MC::initLLVMToSEHAndCVRegMapping(MCRegisterInfo *MRI) {
     codeview::RegisterId CVReg;
     MCPhysReg Reg;
   } RegMap[] = {
-      {codeview::RegisterId::CVRegAL, X86::AL},
-      {codeview::RegisterId::CVRegCL, X86::CL},
-      {codeview::RegisterId::CVRegDL, X86::DL},
-      {codeview::RegisterId::CVRegBL, X86::BL},
-      {codeview::RegisterId::CVRegAH, X86::AH},
-      {codeview::RegisterId::CVRegCH, X86::CH},
-      {codeview::RegisterId::CVRegDH, X86::DH},
-      {codeview::RegisterId::CVRegBH, X86::BH},
-      {codeview::RegisterId::CVRegAX, X86::AX},
-      {codeview::RegisterId::CVRegCX, X86::CX},
-      {codeview::RegisterId::CVRegDX, X86::DX},
-      {codeview::RegisterId::CVRegBX, X86::BX},
-      {codeview::RegisterId::CVRegSP, X86::SP},
-      {codeview::RegisterId::CVRegBP, X86::BP},
-      {codeview::RegisterId::CVRegSI, X86::SI},
-      {codeview::RegisterId::CVRegDI, X86::DI},
-      {codeview::RegisterId::CVRegEAX, X86::EAX},
-      {codeview::RegisterId::CVRegECX, X86::ECX},
-      {codeview::RegisterId::CVRegEDX, X86::EDX},
-      {codeview::RegisterId::CVRegEBX, X86::EBX},
-      {codeview::RegisterId::CVRegESP, X86::ESP},
-      {codeview::RegisterId::CVRegEBP, X86::EBP},
-      {codeview::RegisterId::CVRegESI, X86::ESI},
-      {codeview::RegisterId::CVRegEDI, X86::EDI},
-
-      {codeview::RegisterId::CVRegEFLAGS, X86::EFLAGS},
-
-      {codeview::RegisterId::CVRegST0, X86::FP0},
-      {codeview::RegisterId::CVRegST1, X86::FP1},
-      {codeview::RegisterId::CVRegST2, X86::FP2},
-      {codeview::RegisterId::CVRegST3, X86::FP3},
-      {codeview::RegisterId::CVRegST4, X86::FP4},
-      {codeview::RegisterId::CVRegST5, X86::FP5},
-      {codeview::RegisterId::CVRegST6, X86::FP6},
-      {codeview::RegisterId::CVRegST7, X86::FP7},
-
-      {codeview::RegisterId::CVRegXMM0, X86::XMM0},
-      {codeview::RegisterId::CVRegXMM1, X86::XMM1},
-      {codeview::RegisterId::CVRegXMM2, X86::XMM2},
-      {codeview::RegisterId::CVRegXMM3, X86::XMM3},
-      {codeview::RegisterId::CVRegXMM4, X86::XMM4},
-      {codeview::RegisterId::CVRegXMM5, X86::XMM5},
-      {codeview::RegisterId::CVRegXMM6, X86::XMM6},
-      {codeview::RegisterId::CVRegXMM7, X86::XMM7},
-
-      {codeview::RegisterId::CVRegXMM8, X86::XMM8},
-      {codeview::RegisterId::CVRegXMM9, X86::XMM9},
-      {codeview::RegisterId::CVRegXMM10, X86::XMM10},
-      {codeview::RegisterId::CVRegXMM11, X86::XMM11},
-      {codeview::RegisterId::CVRegXMM12, X86::XMM12},
-      {codeview::RegisterId::CVRegXMM13, X86::XMM13},
-      {codeview::RegisterId::CVRegXMM14, X86::XMM14},
-      {codeview::RegisterId::CVRegXMM15, X86::XMM15},
-
-      {codeview::RegisterId::CVRegSIL, X86::SIL},
-      {codeview::RegisterId::CVRegDIL, X86::DIL},
-      {codeview::RegisterId::CVRegBPL, X86::BPL},
-      {codeview::RegisterId::CVRegSPL, X86::SPL},
-      {codeview::RegisterId::CVRegRAX, X86::RAX},
-      {codeview::RegisterId::CVRegRBX, X86::RBX},
-      {codeview::RegisterId::CVRegRCX, X86::RCX},
-      {codeview::RegisterId::CVRegRDX, X86::RDX},
-      {codeview::RegisterId::CVRegRSI, X86::RSI},
-      {codeview::RegisterId::CVRegRDI, X86::RDI},
-      {codeview::RegisterId::CVRegRBP, X86::RBP},
-      {codeview::RegisterId::CVRegRSP, X86::RSP},
-      {codeview::RegisterId::CVRegR8, X86::R8},
-      {codeview::RegisterId::CVRegR9, X86::R9},
-      {codeview::RegisterId::CVRegR10, X86::R10},
-      {codeview::RegisterId::CVRegR11, X86::R11},
-      {codeview::RegisterId::CVRegR12, X86::R12},
-      {codeview::RegisterId::CVRegR13, X86::R13},
-      {codeview::RegisterId::CVRegR14, X86::R14},
-      {codeview::RegisterId::CVRegR15, X86::R15},
-      {codeview::RegisterId::CVRegR8B, X86::R8B},
-      {codeview::RegisterId::CVRegR9B, X86::R9B},
-      {codeview::RegisterId::CVRegR10B, X86::R10B},
-      {codeview::RegisterId::CVRegR11B, X86::R11B},
-      {codeview::RegisterId::CVRegR12B, X86::R12B},
-      {codeview::RegisterId::CVRegR13B, X86::R13B},
-      {codeview::RegisterId::CVRegR14B, X86::R14B},
-      {codeview::RegisterId::CVRegR15B, X86::R15B},
-      {codeview::RegisterId::CVRegR8W, X86::R8W},
-      {codeview::RegisterId::CVRegR9W, X86::R9W},
-      {codeview::RegisterId::CVRegR10W, X86::R10W},
-      {codeview::RegisterId::CVRegR11W, X86::R11W},
-      {codeview::RegisterId::CVRegR12W, X86::R12W},
-      {codeview::RegisterId::CVRegR13W, X86::R13W},
-      {codeview::RegisterId::CVRegR14W, X86::R14W},
-      {codeview::RegisterId::CVRegR15W, X86::R15W},
-      {codeview::RegisterId::CVRegR8D, X86::R8D},
-      {codeview::RegisterId::CVRegR9D, X86::R9D},
-      {codeview::RegisterId::CVRegR10D, X86::R10D},
-      {codeview::RegisterId::CVRegR11D, X86::R11D},
-      {codeview::RegisterId::CVRegR12D, X86::R12D},
-      {codeview::RegisterId::CVRegR13D, X86::R13D},
-      {codeview::RegisterId::CVRegR14D, X86::R14D},
-      {codeview::RegisterId::CVRegR15D, X86::R15D},
-      {codeview::RegisterId::CVRegAMD64_YMM0, X86::YMM0},
-      {codeview::RegisterId::CVRegAMD64_YMM1, X86::YMM1},
-      {codeview::RegisterId::CVRegAMD64_YMM2, X86::YMM2},
-      {codeview::RegisterId::CVRegAMD64_YMM3, X86::YMM3},
-      {codeview::RegisterId::CVRegAMD64_YMM4, X86::YMM4},
-      {codeview::RegisterId::CVRegAMD64_YMM5, X86::YMM5},
-      {codeview::RegisterId::CVRegAMD64_YMM6, X86::YMM6},
-      {codeview::RegisterId::CVRegAMD64_YMM7, X86::YMM7},
-      {codeview::RegisterId::CVRegAMD64_YMM8, X86::YMM8},
-      {codeview::RegisterId::CVRegAMD64_YMM9, X86::YMM9},
-      {codeview::RegisterId::CVRegAMD64_YMM10, X86::YMM10},
-      {codeview::RegisterId::CVRegAMD64_YMM11, X86::YMM11},
-      {codeview::RegisterId::CVRegAMD64_YMM12, X86::YMM12},
-      {codeview::RegisterId::CVRegAMD64_YMM13, X86::YMM13},
-      {codeview::RegisterId::CVRegAMD64_YMM14, X86::YMM14},
-      {codeview::RegisterId::CVRegAMD64_YMM15, X86::YMM15},
-      {codeview::RegisterId::CVRegAMD64_YMM16, X86::YMM16},
-      {codeview::RegisterId::CVRegAMD64_YMM17, X86::YMM17},
-      {codeview::RegisterId::CVRegAMD64_YMM18, X86::YMM18},
-      {codeview::RegisterId::CVRegAMD64_YMM19, X86::YMM19},
-      {codeview::RegisterId::CVRegAMD64_YMM20, X86::YMM20},
-      {codeview::RegisterId::CVRegAMD64_YMM21, X86::YMM21},
-      {codeview::RegisterId::CVRegAMD64_YMM22, X86::YMM22},
-      {codeview::RegisterId::CVRegAMD64_YMM23, X86::YMM23},
-      {codeview::RegisterId::CVRegAMD64_YMM24, X86::YMM24},
-      {codeview::RegisterId::CVRegAMD64_YMM25, X86::YMM25},
-      {codeview::RegisterId::CVRegAMD64_YMM26, X86::YMM26},
-      {codeview::RegisterId::CVRegAMD64_YMM27, X86::YMM27},
-      {codeview::RegisterId::CVRegAMD64_YMM28, X86::YMM28},
-      {codeview::RegisterId::CVRegAMD64_YMM29, X86::YMM29},
-      {codeview::RegisterId::CVRegAMD64_YMM30, X86::YMM30},
-      {codeview::RegisterId::CVRegAMD64_YMM31, X86::YMM31},
-      {codeview::RegisterId::CVRegAMD64_ZMM0, X86::ZMM0},
-      {codeview::RegisterId::CVRegAMD64_ZMM1, X86::ZMM1},
-      {codeview::RegisterId::CVRegAMD64_ZMM2, X86::ZMM2},
-      {codeview::RegisterId::CVRegAMD64_ZMM3, X86::ZMM3},
-      {codeview::RegisterId::CVRegAMD64_ZMM4, X86::ZMM4},
-      {codeview::RegisterId::CVRegAMD64_ZMM5, X86::ZMM5},
-      {codeview::RegisterId::CVRegAMD64_ZMM6, X86::ZMM6},
-      {codeview::RegisterId::CVRegAMD64_ZMM7, X86::ZMM7},
-      {codeview::RegisterId::CVRegAMD64_ZMM8, X86::ZMM8},
-      {codeview::RegisterId::CVRegAMD64_ZMM9, X86::ZMM9},
-      {codeview::RegisterId::CVRegAMD64_ZMM10, X86::ZMM10},
-      {codeview::RegisterId::CVRegAMD64_ZMM11, X86::ZMM11},
-      {codeview::RegisterId::CVRegAMD64_ZMM12, X86::ZMM12},
-      {codeview::RegisterId::CVRegAMD64_ZMM13, X86::ZMM13},
-      {codeview::RegisterId::CVRegAMD64_ZMM14, X86::ZMM14},
-      {codeview::RegisterId::CVRegAMD64_ZMM15, X86::ZMM15},
-      {codeview::RegisterId::CVRegAMD64_ZMM16, X86::ZMM16},
-      {codeview::RegisterId::CVRegAMD64_ZMM17, X86::ZMM17},
-      {codeview::RegisterId::CVRegAMD64_ZMM18, X86::ZMM18},
-      {codeview::RegisterId::CVRegAMD64_ZMM19, X86::ZMM19},
-      {codeview::RegisterId::CVRegAMD64_ZMM20, X86::ZMM20},
-      {codeview::RegisterId::CVRegAMD64_ZMM21, X86::ZMM21},
-      {codeview::RegisterId::CVRegAMD64_ZMM22, X86::ZMM22},
-      {codeview::RegisterId::CVRegAMD64_ZMM23, X86::ZMM23},
-      {codeview::RegisterId::CVRegAMD64_ZMM24, X86::ZMM24},
-      {codeview::RegisterId::CVRegAMD64_ZMM25, X86::ZMM25},
-      {codeview::RegisterId::CVRegAMD64_ZMM26, X86::ZMM26},
-      {codeview::RegisterId::CVRegAMD64_ZMM27, X86::ZMM27},
-      {codeview::RegisterId::CVRegAMD64_ZMM28, X86::ZMM28},
-      {codeview::RegisterId::CVRegAMD64_ZMM29, X86::ZMM29},
-      {codeview::RegisterId::CVRegAMD64_ZMM30, X86::ZMM30},
-      {codeview::RegisterId::CVRegAMD64_ZMM31, X86::ZMM31},
-      {codeview::RegisterId::CVRegAMD64_K0, X86::K0},
-      {codeview::RegisterId::CVRegAMD64_K1, X86::K1},
-      {codeview::RegisterId::CVRegAMD64_K2, X86::K2},
-      {codeview::RegisterId::CVRegAMD64_K3, X86::K3},
-      {codeview::RegisterId::CVRegAMD64_K4, X86::K4},
-      {codeview::RegisterId::CVRegAMD64_K5, X86::K5},
-      {codeview::RegisterId::CVRegAMD64_K6, X86::K6},
-      {codeview::RegisterId::CVRegAMD64_K7, X86::K7},
+      {codeview::RegisterId::AL, X86::AL},
+      {codeview::RegisterId::CL, X86::CL},
+      {codeview::RegisterId::DL, X86::DL},
+      {codeview::RegisterId::BL, X86::BL},
+      {codeview::RegisterId::AH, X86::AH},
+      {codeview::RegisterId::CH, X86::CH},
+      {codeview::RegisterId::DH, X86::DH},
+      {codeview::RegisterId::BH, X86::BH},
+      {codeview::RegisterId::AX, X86::AX},
+      {codeview::RegisterId::CX, X86::CX},
+      {codeview::RegisterId::DX, X86::DX},
+      {codeview::RegisterId::BX, X86::BX},
+      {codeview::RegisterId::SP, X86::SP},
+      {codeview::RegisterId::BP, X86::BP},
+      {codeview::RegisterId::SI, X86::SI},
+      {codeview::RegisterId::DI, X86::DI},
+      {codeview::RegisterId::EAX, X86::EAX},
+      {codeview::RegisterId::ECX, X86::ECX},
+      {codeview::RegisterId::EDX, X86::EDX},
+      {codeview::RegisterId::EBX, X86::EBX},
+      {codeview::RegisterId::ESP, X86::ESP},
+      {codeview::RegisterId::EBP, X86::EBP},
+      {codeview::RegisterId::ESI, X86::ESI},
+      {codeview::RegisterId::EDI, X86::EDI},
+
+      {codeview::RegisterId::EFLAGS, X86::EFLAGS},
+
+      {codeview::RegisterId::ST0, X86::FP0},
+      {codeview::RegisterId::ST1, X86::FP1},
+      {codeview::RegisterId::ST2, X86::FP2},
+      {codeview::RegisterId::ST3, X86::FP3},
+      {codeview::RegisterId::ST4, X86::FP4},
+      {codeview::RegisterId::ST5, X86::FP5},
+      {codeview::RegisterId::ST6, X86::FP6},
+      {codeview::RegisterId::ST7, X86::FP7},
+
+      {codeview::RegisterId::XMM0, X86::XMM0},
+      {codeview::RegisterId::XMM1, X86::XMM1},
+      {codeview::RegisterId::XMM2, X86::XMM2},
+      {codeview::RegisterId::XMM3, X86::XMM3},
+      {codeview::RegisterId::XMM4, X86::XMM4},
+      {codeview::RegisterId::XMM5, X86::XMM5},
+      {codeview::RegisterId::XMM6, X86::XMM6},
+      {codeview::RegisterId::XMM7, X86::XMM7},
+
+      {codeview::RegisterId::XMM8, X86::XMM8},
+      {codeview::RegisterId::XMM9, X86::XMM9},
+      {codeview::RegisterId::XMM10, X86::XMM10},
+      {codeview::RegisterId::XMM11, X86::XMM11},
+      {codeview::RegisterId::XMM12, X86::XMM12},
+      {codeview::RegisterId::XMM13, X86::XMM13},
+      {codeview::RegisterId::XMM14, X86::XMM14},
+      {codeview::RegisterId::XMM15, X86::XMM15},
+
+      {codeview::RegisterId::SIL, X86::SIL},
+      {codeview::RegisterId::DIL, X86::DIL},
+      {codeview::RegisterId::BPL, X86::BPL},
+      {codeview::RegisterId::SPL, X86::SPL},
+      {codeview::RegisterId::RAX, X86::RAX},
+      {codeview::RegisterId::RBX, X86::RBX},
+      {codeview::RegisterId::RCX, X86::RCX},
+      {codeview::RegisterId::RDX, X86::RDX},
+      {codeview::RegisterId::RSI, X86::RSI},
+      {codeview::RegisterId::RDI, X86::RDI},
+      {codeview::RegisterId::RBP, X86::RBP},
+      {codeview::RegisterId::RSP, X86::RSP},
+      {codeview::RegisterId::R8, X86::R8},
+      {codeview::RegisterId::R9, X86::R9},
+      {codeview::RegisterId::R10, X86::R10},
+      {codeview::RegisterId::R11, X86::R11},
+      {codeview::RegisterId::R12, X86::R12},
+      {codeview::RegisterId::R13, X86::R13},
+      {codeview::RegisterId::R14, X86::R14},
+      {codeview::RegisterId::R15, X86::R15},
+      {codeview::RegisterId::R8B, X86::R8B},
+      {codeview::RegisterId::R9B, X86::R9B},
+      {codeview::RegisterId::R10B, X86::R10B},
+      {codeview::RegisterId::R11B, X86::R11B},
+      {codeview::RegisterId::R12B, X86::R12B},
+      {codeview::RegisterId::R13B, X86::R13B},
+      {codeview::RegisterId::R14B, X86::R14B},
+      {codeview::RegisterId::R15B, X86::R15B},
+      {codeview::RegisterId::R8W, X86::R8W},
+      {codeview::RegisterId::R9W, X86::R9W},
+      {codeview::RegisterId::R10W, X86::R10W},
+      {codeview::RegisterId::R11W, X86::R11W},
+      {codeview::RegisterId::R12W, X86::R12W},
+      {codeview::RegisterId::R13W, X86::R13W},
+      {codeview::RegisterId::R14W, X86::R14W},
+      {codeview::RegisterId::R15W, X86::R15W},
+      {codeview::RegisterId::R8D, X86::R8D},
+      {codeview::RegisterId::R9D, X86::R9D},
+      {codeview::RegisterId::R10D, X86::R10D},
+      {codeview::RegisterId::R11D, X86::R11D},
+      {codeview::RegisterId::R12D, X86::R12D},
+      {codeview::RegisterId::R13D, X86::R13D},
+      {codeview::RegisterId::R14D, X86::R14D},
+      {codeview::RegisterId::R15D, X86::R15D},
+      {codeview::RegisterId::AMD64_YMM0, X86::YMM0},
+      {codeview::RegisterId::AMD64_YMM1, X86::YMM1},
+      {codeview::RegisterId::AMD64_YMM2, X86::YMM2},
+      {codeview::RegisterId::AMD64_YMM3, X86::YMM3},
+      {codeview::RegisterId::AMD64_YMM4, X86::YMM4},
+      {codeview::RegisterId::AMD64_YMM5, X86::YMM5},
+      {codeview::RegisterId::AMD64_YMM6, X86::YMM6},
+      {codeview::RegisterId::AMD64_YMM7, X86::YMM7},
+      {codeview::RegisterId::AMD64_YMM8, X86::YMM8},
+      {codeview::RegisterId::AMD64_YMM9, X86::YMM9},
+      {codeview::RegisterId::AMD64_YMM10, X86::YMM10},
+      {codeview::RegisterId::AMD64_YMM11, X86::YMM11},
+      {codeview::RegisterId::AMD64_YMM12, X86::YMM12},
+      {codeview::RegisterId::AMD64_YMM13, X86::YMM13},
+      {codeview::RegisterId::AMD64_YMM14, X86::YMM14},
+      {codeview::RegisterId::AMD64_YMM15, X86::YMM15},
+      {codeview::RegisterId::AMD64_YMM16, X86::YMM16},
+      {codeview::RegisterId::AMD64_YMM17, X86::YMM17},
+      {codeview::RegisterId::AMD64_YMM18, X86::YMM18},
+      {codeview::RegisterId::AMD64_YMM19, X86::YMM19},
+      {codeview::RegisterId::AMD64_YMM20, X86::YMM20},
+      {codeview::RegisterId::AMD64_YMM21, X86::YMM21},
+      {codeview::RegisterId::AMD64_YMM22, X86::YMM22},
+      {codeview::RegisterId::AMD64_YMM23, X86::YMM23},
+      {codeview::RegisterId::AMD64_YMM24, X86::YMM24},
+      {codeview::RegisterId::AMD64_YMM25, X86::YMM25},
+      {codeview::RegisterId::AMD64_YMM26, X86::YMM26},
+      {codeview::RegisterId::AMD64_YMM27, X86::YMM27},
+      {codeview::RegisterId::AMD64_YMM28, X86::YMM28},
+      {codeview::RegisterId::AMD64_YMM29, X86::YMM29},
+      {codeview::RegisterId::AMD64_YMM30, X86::YMM30},
+      {codeview::RegisterId::AMD64_YMM31, X86::YMM31},
+      {codeview::RegisterId::AMD64_ZMM0, X86::ZMM0},
+      {codeview::RegisterId::AMD64_ZMM1, X86::ZMM1},
+      {codeview::RegisterId::AMD64_ZMM2, X86::ZMM2},
+      {codeview::RegisterId::AMD64_ZMM3, X86::ZMM3},
+      {codeview::RegisterId::AMD64_ZMM4, X86::ZMM4},
+      {codeview::RegisterId::AMD64_ZMM5, X86::ZMM5},
+      {codeview::RegisterId::AMD64_ZMM6, X86::ZMM6},
+      {codeview::RegisterId::AMD64_ZMM7, X86::ZMM7},
+      {codeview::RegisterId::AMD64_ZMM8, X86::ZMM8},
+      {codeview::RegisterId::AMD64_ZMM9, X86::ZMM9},
+      {codeview::RegisterId::AMD64_ZMM10, X86::ZMM10},
+      {codeview::RegisterId::AMD64_ZMM11, X86::ZMM11},
+      {codeview::RegisterId::AMD64_ZMM12, X86::ZMM12},
+      {codeview::RegisterId::AMD64_ZMM13, X86::ZMM13},
+      {codeview::RegisterId::AMD64_ZMM14, X86::ZMM14},
+      {codeview::RegisterId::AMD64_ZMM15, X86::ZMM15},
+      {codeview::RegisterId::AMD64_ZMM16, X86::ZMM16},
+      {codeview::RegisterId::AMD64_ZMM17, X86::ZMM17},
+      {codeview::RegisterId::AMD64_ZMM18, X86::ZMM18},
+      {codeview::RegisterId::AMD64_ZMM19, X86::ZMM19},
+      {codeview::RegisterId::AMD64_ZMM20, X86::ZMM20},
+      {codeview::RegisterId::AMD64_ZMM21, X86::ZMM21},
+      {codeview::RegisterId::AMD64_ZMM22, X86::ZMM22},
+      {codeview::RegisterId::AMD64_ZMM23, X86::ZMM23},
+      {codeview::RegisterId::AMD64_ZMM24, X86::ZMM24},
+      {codeview::RegisterId::AMD64_ZMM25, X86::ZMM25},
+      {codeview::RegisterId::AMD64_ZMM26, X86::ZMM26},
+      {codeview::RegisterId::AMD64_ZMM27, X86::ZMM27},
+      {codeview::RegisterId::AMD64_ZMM28, X86::ZMM28},
+      {codeview::RegisterId::AMD64_ZMM29, X86::ZMM29},
+      {codeview::RegisterId::AMD64_ZMM30, X86::ZMM30},
+      {codeview::RegisterId::AMD64_ZMM31, X86::ZMM31},
+      {codeview::RegisterId::AMD64_K0, X86::K0},
+      {codeview::RegisterId::AMD64_K1, X86::K1},
+      {codeview::RegisterId::AMD64_K2, X86::K2},
+      {codeview::RegisterId::AMD64_K3, X86::K3},
+      {codeview::RegisterId::AMD64_K4, X86::K4},
+      {codeview::RegisterId::AMD64_K5, X86::K5},
+      {codeview::RegisterId::AMD64_K6, X86::K6},
+      {codeview::RegisterId::AMD64_K7, X86::K7},
   };
   for (unsigned I = 0; I < array_lengthof(RegMap); ++I)
     MRI->mapLLVMRegToCVReg(RegMap[I].Reg, static_cast<int>(RegMap[I].CVReg));