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| author | Sjoerd Meijer <sjoerd.meijer@arm.com> | 2018-03-07 09:10:44 +0000 |
|---|---|---|
| committer | Sjoerd Meijer <sjoerd.meijer@arm.com> | 2018-03-07 09:10:44 +0000 |
| commit | af30f06d5c56b556f8b1b055ffec9f40604733d3 (patch) | |
| tree | 7558688dc20c8657e7facdc28cb3c22eb6f95b3c /llvm/lib | |
| parent | 91c853a79d68761c610b7ac2f183f0a401b48df3 (diff) | |
| download | bcm5719-llvm-af30f06d5c56b556f8b1b055ffec9f40604733d3.tar.gz bcm5719-llvm-af30f06d5c56b556f8b1b055ffec9f40604733d3.zip | |
[ARM] Fix for PR36577
Don't PerformSHLSimplify if the given node is used by a node that also uses a
constant because we may get stuck in an infinite combine loop.
bugzilla: https://bugs.llvm.org/show_bug.cgi?id=36577
Patch by Sam Parker.
Differential Revision: https://reviews.llvm.org/D44097
llvm-svn: 326882
Diffstat (limited to 'llvm/lib')
| -rw-r--r-- | llvm/lib/Target/ARM/ARMISelLowering.cpp | 25 |
1 files changed, 17 insertions, 8 deletions
diff --git a/llvm/lib/Target/ARM/ARMISelLowering.cpp b/llvm/lib/Target/ARM/ARMISelLowering.cpp index 4cdc064838f..0c9f615d888 100644 --- a/llvm/lib/Target/ARM/ARMISelLowering.cpp +++ b/llvm/lib/Target/ARM/ARMISelLowering.cpp @@ -10442,7 +10442,14 @@ static SDValue PerformSHLSimplify(SDNode *N, case ISD::XOR: case ISD::SETCC: case ARMISD::CMP: - // Check that its not already using a shl. + // Check that the user isn't already using a constant because there + // aren't any instructions that support an immediate operand and a + // shifted operand. + if (isa<ConstantSDNode>(U->getOperand(0)) || + isa<ConstantSDNode>(U->getOperand(1))) + return SDValue(); + + // Check that it's not already using a shift. if (U->getOperand(0).getOpcode() == ISD::SHL || U->getOperand(1).getOpcode() == ISD::SHL) return SDValue(); @@ -10464,8 +10471,6 @@ static SDValue PerformSHLSimplify(SDNode *N, if (!C1ShlC2 || !C2) return SDValue(); - DEBUG(dbgs() << "Trying to simplify shl: "; N->dump()); - APInt C2Int = C2->getAPIntValue(); APInt C1Int = C1ShlC2->getAPIntValue(); @@ -10479,12 +10484,12 @@ static SDValue PerformSHLSimplify(SDNode *N, C1Int.lshrInPlace(C2Int); // The immediates are encoded as an 8-bit value that can be rotated. - unsigned Zeros = C1Int.countLeadingZeros() + C1Int.countTrailingZeros(); - if (C1Int.getBitWidth() - Zeros > 8) - return SDValue(); + auto LargeImm = [](const APInt &Imm) { + unsigned Zeros = Imm.countLeadingZeros() + Imm.countTrailingZeros(); + return Imm.getBitWidth() - Zeros > 8; + }; - Zeros = C2Int.countLeadingZeros() + C2Int.countTrailingZeros(); - if (C2Int.getBitWidth() - Zeros > 8) + if (LargeImm(C1Int) || LargeImm(C2Int)) return SDValue(); SelectionDAG &DAG = DCI.DAG; @@ -10495,6 +10500,10 @@ static SDValue PerformSHLSimplify(SDNode *N, // Shift left to compensate for the lshr of C1Int. SDValue Res = DAG.getNode(ISD::SHL, dl, MVT::i32, BinOp, SHL.getOperand(1)); + DEBUG(dbgs() << "Simplify shl use:\n"; SHL.getOperand(0).dump(); SHL.dump(); + N->dump()); + DEBUG(dbgs() << "Into:\n"; X.dump(); BinOp.dump(); Res.dump()); + DAG.ReplaceAllUsesWith(SDValue(N, 0), Res); return SDValue(N, 0); } |

