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authorEric Christopher <echristo@gmail.com>2014-07-03 00:44:28 +0000
committerEric Christopher <echristo@gmail.com>2014-07-03 00:44:28 +0000
commitad4de684ea3a500c7c7b264fe819801e6a58433f (patch)
tree075f9537b01680f2c82a1f3a2c7346f8c2315010 /llvm/lib
parent5752ad0abcd362ce17af6c8dfeb73672ade4a3f2 (diff)
downloadbcm5719-llvm-ad4de684ea3a500c7c7b264fe819801e6a58433f.tar.gz
bcm5719-llvm-ad4de684ea3a500c7c7b264fe819801e6a58433f.zip
Remove dead code.
llvm-svn: 212244
Diffstat (limited to 'llvm/lib')
-rw-r--r--llvm/lib/Target/Mips/Mips16ISelLowering.cpp7
1 files changed, 0 insertions, 7 deletions
diff --git a/llvm/lib/Target/Mips/Mips16ISelLowering.cpp b/llvm/lib/Target/Mips/Mips16ISelLowering.cpp
index 9102450dc53..81a05df1a70 100644
--- a/llvm/lib/Target/Mips/Mips16ISelLowering.cpp
+++ b/llvm/lib/Target/Mips/Mips16ISelLowering.cpp
@@ -120,13 +120,6 @@ static const Mips16IntrinsicHelperType Mips16IntrinsicHelper[] = {
Mips16TargetLowering::Mips16TargetLowering(MipsTargetMachine &TM)
: MipsTargetLowering(TM) {
- //
- // set up as if mips32 and then revert so we can test the mechanism
- // for switching
- addRegisterClass(MVT::i32, &Mips::GPR32RegClass);
- addRegisterClass(MVT::f32, &Mips::FGR32RegClass);
- computeRegisterProperties();
- clearRegisterClasses();
// Set up the register classes
addRegisterClass(MVT::i32, &Mips::CPU16RegsRegClass);
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