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authorMatt Arsenault <Matthew.Arsenault@amd.com>2014-09-21 17:27:32 +0000
committerMatt Arsenault <Matthew.Arsenault@amd.com>2014-09-21 17:27:32 +0000
commita9627ae97a103170ee2441f3cbf884629740a332 (patch)
tree01df690b589319986ee4eab54363ece567f6c546 /llvm/lib
parent393366c691b69550fd95d1f552ff4d5a016f98bd (diff)
downloadbcm5719-llvm-a9627ae97a103170ee2441f3cbf884629740a332.tar.gz
bcm5719-llvm-a9627ae97a103170ee2441f3cbf884629740a332.zip
Fix typo
llvm-svn: 218223
Diffstat (limited to 'llvm/lib')
-rw-r--r--llvm/lib/Target/R600/SIShrinkInstructions.cpp7
1 files changed, 3 insertions, 4 deletions
diff --git a/llvm/lib/Target/R600/SIShrinkInstructions.cpp b/llvm/lib/Target/R600/SIShrinkInstructions.cpp
index 821c0543495..5eaf4a54b4b 100644
--- a/llvm/lib/Target/R600/SIShrinkInstructions.cpp
+++ b/llvm/lib/Target/R600/SIShrinkInstructions.cpp
@@ -221,10 +221,9 @@ bool SIShrinkInstructions::runOnMachineFunction(MachineFunction &MF) {
// vreg1 = VOPC;
// S_AND_B64 vreg0, vreg1
//
- // So, instead of forcing the instruction to write to VCC, we provide a
- // hint to the register allocator to use VCC and then we
- // we will run this pass again after RA and shrink it if it outpus to
- // VCC.
+ // So, instead of forcing the instruction to write to VCC, we provide
+ // a hint to the register allocator to use VCC and then we we will run
+ // this pass again after RA and shrink it if it outputs to VCC.
MRI.setRegAllocationHint(MI.getOperand(0).getReg(), 0, AMDGPU::VCC);
continue;
}
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