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| author | Oliver Cruickshank <oliver.cruickshank@arm.com> | 2019-09-16 15:19:56 +0000 |
|---|---|---|
| committer | Oliver Cruickshank <oliver.cruickshank@arm.com> | 2019-09-16 15:19:56 +0000 |
| commit | 5f799ef1627f6f4f548f411a40fb94c620af25b6 (patch) | |
| tree | 6165f0798a07f4266bab061ae99a88063b0bbe7f /llvm/lib | |
| parent | cd1a0b92710e567c00f6d2b932b197e9a1773f7d (diff) | |
| download | bcm5719-llvm-5f799ef1627f6f4f548f411a40fb94c620af25b6.tar.gz bcm5719-llvm-5f799ef1627f6f4f548f411a40fb94c620af25b6.zip | |
[ARM] Lower CTTZ on MVE
Lower CTTZ on MVE using VBRSR and VCLS which will reverse the bits and
count the leading zeros, equivalent to a count trailing zeros (CTTZ).
llvm-svn: 372000
Diffstat (limited to 'llvm/lib')
| -rw-r--r-- | llvm/lib/Target/ARM/ARMISelLowering.cpp | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/llvm/lib/Target/ARM/ARMISelLowering.cpp b/llvm/lib/Target/ARM/ARMISelLowering.cpp index f7d5496303a..d8e3b0973b9 100644 --- a/llvm/lib/Target/ARM/ARMISelLowering.cpp +++ b/llvm/lib/Target/ARM/ARMISelLowering.cpp @@ -262,6 +262,7 @@ void ARMTargetLowering::addMVEVectorTypes(bool HasMVEFP) { setOperationAction(ISD::MLOAD, VT, Custom); setOperationAction(ISD::MSTORE, VT, Legal); setOperationAction(ISD::CTLZ, VT, Legal); + setOperationAction(ISD::CTTZ, VT, Expand); // No native support for these. setOperationAction(ISD::UDIV, VT, Expand); @@ -5805,8 +5806,7 @@ static SDValue LowerCTTZ(SDNode *N, SelectionDAG &DAG, const ARMSubtarget *ST) { SDLoc dl(N); EVT VT = N->getValueType(0); - if (VT.isVector()) { - assert(ST->hasNEON()); + if (VT.isVector() && ST->hasNEON()) { // Compute the least significant set bit: LSB = X & -X SDValue X = N->getOperand(0); |
