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| author | Chris Lattner <sabre@nondot.org> | 2006-03-22 01:44:36 +0000 |
|---|---|---|
| committer | Chris Lattner <sabre@nondot.org> | 2006-03-22 01:44:36 +0000 |
| commit | 4e7371758fedc08d931b837ff808c9c2e6b3822c (patch) | |
| tree | 03504c40adc93168f11514ac5b76ef079fd68c86 /llvm/lib | |
| parent | 5be4352124ad611b2b839124d64e4024bdbf429d (diff) | |
| download | bcm5719-llvm-4e7371758fedc08d931b837ff808c9c2e6b3822c.tar.gz bcm5719-llvm-4e7371758fedc08d931b837ff808c9c2e6b3822c.zip | |
Fix the JIT encoding of the VAForm_1 instructions, including vmaddfp
llvm-svn: 26935
Diffstat (limited to 'llvm/lib')
| -rw-r--r-- | llvm/lib/Target/PowerPC/PPCInstrFormats.td | 2 | ||||
| -rw-r--r-- | llvm/lib/Target/PowerPC/PPCInstrInfo.td | 15 |
2 files changed, 8 insertions, 9 deletions
diff --git a/llvm/lib/Target/PowerPC/PPCInstrFormats.td b/llvm/lib/Target/PowerPC/PPCInstrFormats.td index be0b262783f..868771a1676 100644 --- a/llvm/lib/Target/PowerPC/PPCInstrFormats.td +++ b/llvm/lib/Target/PowerPC/PPCInstrFormats.td @@ -595,8 +595,8 @@ class VAForm_1<bits<6> xo, dag OL, string asmstr, : I<4, OL, asmstr, itin> { bits<5> VD; bits<5> VA; - bits<5> VB; bits<5> VC; + bits<5> VB; let Pattern = pattern; diff --git a/llvm/lib/Target/PowerPC/PPCInstrInfo.td b/llvm/lib/Target/PowerPC/PPCInstrInfo.td index 3d0a30d0a85..181f1565640 100644 --- a/llvm/lib/Target/PowerPC/PPCInstrInfo.td +++ b/llvm/lib/Target/PowerPC/PPCInstrInfo.td @@ -948,22 +948,21 @@ def RLDICR : MDForm_1<30, 1, let PPC970_Unit = 5 in { // VALU Operations. // VA-Form instructions. 3-input AltiVec ops. -def VMADDFP : VAForm_1<46, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB, VRRC:$vC), +def VMADDFP : VAForm_1<46, (ops VRRC:$vD, VRRC:$vA, VRRC:$vC, VRRC:$vB), "vmaddfp $vD, $vA, $vC, $vB", VecFP, [(set VRRC:$vD, (fadd (fmul VRRC:$vA, VRRC:$vC), VRRC:$vB))]>, Requires<[FPContractions]>; -def VNMSUBFP: VAForm_1<47, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB, VRRC:$vC), +def VNMSUBFP: VAForm_1<47, (ops VRRC:$vD, VRRC:$vA, VRRC:$vC, VRRC:$vB), "vnmsubfp $vD, $vA, $vC, $vB", VecFP, - [(set VRRC:$vD, (fneg (fsub (fmul VRRC:$vA, - VRRC:$vC), - VRRC:$vB)))]>, + [(set VRRC:$vD, (fneg (fsub (fmul VRRC:$vA, VRRC:$vC), + VRRC:$vB)))]>, Requires<[FPContractions]>; -def VPERM : VAForm_1<43, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB, VRRC:$vC), - "vperm $vD, $vA, $vB, $vC", VecPerm, +def VPERM : VAForm_1<43, (ops VRRC:$vD, VRRC:$vA, VRRC:$vC, VRRC:$vB), + "vperm $vD, $vA, $vC, $vB", VecPerm, [(set VRRC:$vD, - (PPCvperm (v4f32 VRRC:$vA), VRRC:$vB, VRRC:$vC))]>; + (PPCvperm (v4f32 VRRC:$vA), VRRC:$vC, VRRC:$vB))]>; // VX-Form instructions. AltiVec arithmetic ops. |
