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| author | Alexander Timofeev <Alexander.Timofeev@amd.com> | 2019-05-27 15:03:29 +0000 |
|---|---|---|
| committer | Alexander Timofeev <Alexander.Timofeev@amd.com> | 2019-05-27 15:03:29 +0000 |
| commit | 4a7c4069aeebaf98e6f0508732594383dcd9f051 (patch) | |
| tree | 6231e02220ce6c5aa4227c4d075fda1f0f2992cd /llvm/lib | |
| parent | e091ab1b2df75b73815c22d0869e9f041679c09a (diff) | |
| download | bcm5719-llvm-4a7c4069aeebaf98e6f0508732594383dcd9f051.tar.gz bcm5719-llvm-4a7c4069aeebaf98e6f0508732594383dcd9f051.zip | |
[AMDGPU] Fix for the address sanitizer failure caused by the ifollowing commit:
1a8b2ea611cf4ca7cb09562e0238cfefa27c05b5 Divergence driven ISel. Assign register class for cross block values according to the divergence.
llvm-svn: 361770
Diffstat (limited to 'llvm/lib')
| -rw-r--r-- | llvm/lib/Target/AMDGPU/SIFixSGPRCopies.cpp | 4 |
1 files changed, 3 insertions, 1 deletions
diff --git a/llvm/lib/Target/AMDGPU/SIFixSGPRCopies.cpp b/llvm/lib/Target/AMDGPU/SIFixSGPRCopies.cpp index 8ad7a52c92b..4fd28fc6d81 100644 --- a/llvm/lib/Target/AMDGPU/SIFixSGPRCopies.cpp +++ b/llvm/lib/Target/AMDGPU/SIFixSGPRCopies.cpp @@ -595,7 +595,9 @@ bool SIFixSGPRCopies::runOnMachineFunction(MachineFunction &MF) { unsigned OpNo = UseMI->getOperandNo(&Use); const MCInstrDesc &Desc = TII->get(UseMI->getOpcode()); - if (Desc.OpInfo && Desc.OpInfo[OpNo].RegClass != -1) { + if (!Desc.isPseudo() && Desc.OpInfo && + OpNo <= Desc.getNumOperands() && + Desc.OpInfo[OpNo].RegClass != -1) { const TargetRegisterClass *OpRC = TRI->getRegClass(Desc.OpInfo[OpNo].RegClass); if (!TRI->isSGPRClass(OpRC) && OpRC != &AMDGPU::VS_32RegClass && |
