Move if-conversion before post-regalloc scheduling so the predicated instruction get scheduled properly.

llvm-svn: 84843

1 files changed, 3 insertions, 5 deletions

diff --git a/llvm/lib/Target/ARM/ARMTargetMachine.cpp b/llvm/lib/Target/ARM/ARMTargetMachine.cpp
index c1da6ce88b9..bd2e7347d4f 100644
--- a/llvm/lib/Target/ARM/ARMTargetMachine.cpp
+++ b/llvm/lib/Target/ARM/ARMTargetMachine.cpp
@@ -103,18 +103,16 @@ bool ARMBaseTargetMachine::addPreRegAlloc(PassManagerBase &PM,
 bool ARMBaseTargetMachine::addPreSched2(PassManagerBase &PM,
                                         CodeGenOpt::Level OptLevel) {
   // FIXME: temporarily disabling load / store optimization pass for Thumb1.
-  if (OptLevel != CodeGenOpt::None && !Subtarget.isThumb1Only())
+  if (OptLevel != CodeGenOpt::None && !Subtarget.isThumb1Only()) {
     PM.add(createARMLoadStoreOptimizationPass());
+    PM.add(createIfConverterPass());
+  }
 
   return true;
 }
 
 bool ARMBaseTargetMachine::addPreEmitPass(PassManagerBase &PM,
                                           CodeGenOpt::Level OptLevel) {
-  // FIXME: temporarily disabling load / store optimization pass for Thumb1.
-  if (OptLevel != CodeGenOpt::None && !Subtarget.isThumb1Only())
-    PM.add(createIfConverterPass());
-
   if (Subtarget.isThumb2()) {
     PM.add(createThumb2ITBlockPass());
     PM.add(createThumb2SizeReductionPass());