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| author | Geoff Berry <gberry@codeaurora.org> | 2016-02-23 19:34:13 +0000 |
|---|---|---|
| committer | Geoff Berry <gberry@codeaurora.org> | 2016-02-23 19:34:13 +0000 |
| commit | 27b1ded41ac1ef82536ebee78afceedfb7c9a0c8 (patch) | |
| tree | dbd7f6b7c90131fa9f6f80f1ffcc448e48765114 /llvm/lib | |
| parent | 5a459f8249e02bfc09aff0c0e8d33a9e1866dd8c (diff) | |
| download | bcm5719-llvm-27b1ded41ac1ef82536ebee78afceedfb7c9a0c8.tar.gz bcm5719-llvm-27b1ded41ac1ef82536ebee78afceedfb7c9a0c8.zip | |
[AArch64] Generate csinv instruction more often
Reviewers: t.p.northover, jmolloy
Subscribers: aemerson, rengolin, mcrosier, llvm-commits
Differential Revision: http://reviews.llvm.org/D17546
llvm-svn: 261675
Diffstat (limited to 'llvm/lib')
| -rw-r--r-- | llvm/lib/Target/AArch64/AArch64InstrInfo.td | 8 |
1 files changed, 8 insertions, 0 deletions
diff --git a/llvm/lib/Target/AArch64/AArch64InstrInfo.td b/llvm/lib/Target/AArch64/AArch64InstrInfo.td index 9ca00949a68..c98db1c7afb 100644 --- a/llvm/lib/Target/AArch64/AArch64InstrInfo.td +++ b/llvm/lib/Target/AArch64/AArch64InstrInfo.td @@ -1129,6 +1129,14 @@ def : Pat<(AArch64csel (i32 0), (i32 -1), (i32 imm:$cc), NZCV), (CSINVWr WZR, WZR, (i32 imm:$cc))>; def : Pat<(AArch64csel (i64 0), (i64 -1), (i32 imm:$cc), NZCV), (CSINVXr XZR, XZR, (i32 imm:$cc))>; +def : Pat<(AArch64csel GPR32:$tval, (i32 -1), (i32 imm:$cc), NZCV), + (CSINVWr GPR32:$tval, WZR, (i32 imm:$cc))>; +def : Pat<(AArch64csel GPR64:$tval, (i64 -1), (i32 imm:$cc), NZCV), + (CSINVXr GPR64:$tval, XZR, (i32 imm:$cc))>; +def : Pat<(AArch64csel (i32 -1), GPR32:$fval, (i32 imm:$cc), NZCV), + (CSINVWr GPR32:$fval, WZR, (i32 (inv_cond_XFORM imm:$cc)))>; +def : Pat<(AArch64csel (i64 -1), GPR64:$fval, (i32 imm:$cc), NZCV), + (CSINVXr GPR64:$fval, XZR, (i32 (inv_cond_XFORM imm:$cc)))>; // The inverse of the condition code from the alias instruction is what is used // in the aliased instruction. The parser all ready inverts the condition code |
