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authorChad Rosier <mcrosier@codeaurora.org>2016-05-12 19:51:58 +0000
committerChad Rosier <mcrosier@codeaurora.org>2016-05-12 19:51:58 +0000
commit179480a4ea2552952b2bd98e7d199aacb29cde3b (patch)
tree46858acf49f932b35acbfc2cd6ad432a9fa62ef7 /llvm/lib
parent98de80529a170aa90ffdcb519aeab622573414ad (diff)
downloadbcm5719-llvm-179480a4ea2552952b2bd98e7d199aacb29cde3b.tar.gz
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[AArch64] Give function a more appropriate name.
llvm-svn: 269335
Diffstat (limited to 'llvm/lib')
-rw-r--r--llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp6
1 files changed, 3 insertions, 3 deletions
diff --git a/llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp b/llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp
index a16e8f08057..c833a92de67 100644
--- a/llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp
+++ b/llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp
@@ -1984,8 +1984,8 @@ static bool isBitfieldPositioningOp(SelectionDAG *CurDAG, SDValue Op,
// if yes, given reference arguments will be update so that one can replace
// the OR instruction with:
// f = Opc Opd0, Opd1, LSB, MSB ; where Opc is a BFM, LSB = imm, and MSB = imm2
-static SDNode *isBitfieldInsertOpFromOr(SDNode *N, const APInt &UsefulBits,
- SelectionDAG *CurDAG) {
+static SDNode *selectBitfieldInsertOpFromOr(SDNode *N, const APInt &UsefulBits,
+ SelectionDAG *CurDAG) {
assert(N->getOpcode() == ISD::OR && "Expect a OR operation");
SDValue Dst, Src;
@@ -2098,7 +2098,7 @@ SDNode *AArch64DAGToDAGISel::SelectBitfieldInsertOp(SDNode *N) {
return CurDAG->SelectNodeTo(N, TargetOpcode::IMPLICIT_DEF,
N->getValueType(0));
- return isBitfieldInsertOpFromOr(N, NUsefulBits, CurDAG);
+ return selectBitfieldInsertOpFromOr(N, NUsefulBits, CurDAG);
}
/// SelectBitfieldInsertInZeroOp - Match a UBFIZ instruction that is the
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