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| author | Akira Hatanaka <ahatanaka@mips.com> | 2011-11-07 21:32:58 +0000 |
|---|---|---|
| committer | Akira Hatanaka <ahatanaka@mips.com> | 2011-11-07 21:32:58 +0000 |
| commit | 1537e297e1ea29509c909d713de0305d2234b37a (patch) | |
| tree | d0cd884330ee893a0d469b933100c5da2a5f4702 /llvm/lib | |
| parent | 44dcc589b3aa39eae018bde2ae36b238312f82e2 (diff) | |
| download | bcm5719-llvm-1537e297e1ea29509c909d713de0305d2234b37a.tar.gz bcm5719-llvm-1537e297e1ea29509c909d713de0305d2234b37a.zip | |
Add definitions of 64-bit instructions which move data between integer and
floating pointer registers.
llvm-svn: 144016
Diffstat (limited to 'llvm/lib')
| -rw-r--r-- | llvm/lib/Target/Mips/MipsInstrFPU.td | 8 |
1 files changed, 8 insertions, 0 deletions
diff --git a/llvm/lib/Target/Mips/MipsInstrFPU.td b/llvm/lib/Target/Mips/MipsInstrFPU.td index 62cee12543d..0778c3d1541 100644 --- a/llvm/lib/Target/Mips/MipsInstrFPU.td +++ b/llvm/lib/Target/Mips/MipsInstrFPU.td @@ -183,6 +183,14 @@ def MTC1 : FFRGPR<0x04, (outs FGR32:$fs), (ins CPURegs:$rt), "mtc1\t$rt, $fs", [(set FGR32:$fs, (bitconvert CPURegs:$rt))]>; +def DMFC1 : FFRGPR<0x01, (outs CPU64Regs:$rt), (ins FGR64:$fs), + "dmfc1\t$rt, $fs", + [(set CPU64Regs:$rt, (bitconvert FGR64:$fs))]>; + +def DMTC1 : FFRGPR<0x05, (outs FGR64:$fs), (ins CPU64Regs:$rt), + "dmtc1\t$rt, $fs", + [(set FGR64:$fs, (bitconvert CPU64Regs:$rt))]>; + def FMOV_S : FFR1<0x6, 16, "mov", "s", FGR32, FGR32>; def FMOV_D32 : FFR1<0x6, 17, "mov", "d", AFGR64, AFGR64>, Requires<[NotFP64bit]>; |
