summaryrefslogtreecommitdiffstats
path: root/llvm/lib
diff options
context:
space:
mode:
authorRenato Golin <renato.golin@linaro.org>2014-03-26 12:52:28 +0000
committerRenato Golin <renato.golin@linaro.org>2014-03-26 12:52:28 +0000
commitc0a3c1d66b479b4e1e72e70d65bbfb2ee66c16f6 (patch)
tree5af7c84d2f3007ac25b226f0c18503db70f08cf3 /llvm/lib
parent732f0f73a732a6dbde036003cbaed24ce58c66a5 (diff)
downloadbcm5719-llvm-c0a3c1d66b479b4e1e72e70d65bbfb2ee66c16f6.tar.gz
bcm5719-llvm-c0a3c1d66b479b4e1e72e70d65bbfb2ee66c16f6.zip
Add @llvm.clear_cache builtin
Implementing the LLVM part of the call to __builtin___clear_cache which translates into an intrinsic @llvm.clear_cache and is lowered by each target, either to a call to __clear_cache or nothing at all incase the caches are unified. Updating LangRef and adding some tests for the implemented architectures. Other archs will have to implement the method in case this builtin has to be compiled for it, since the default behaviour is to bail unimplemented. A Clang patch is required for the builtin to be lowered into the llvm intrinsic. This will be done next. llvm-svn: 204802
Diffstat (limited to 'llvm/lib')
-rw-r--r--llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp2
-rw-r--r--llvm/lib/Target/ARM/ARMISelLowering.h5
-rw-r--r--llvm/lib/Target/Mips/MipsISelLowering.h5
-rw-r--r--llvm/lib/Target/X86/X86ISelLowering.h5
4 files changed, 17 insertions, 0 deletions
diff --git a/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp b/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
index bd80a503e21..639ff82ffd3 100644
--- a/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
@@ -5386,6 +5386,8 @@ SelectionDAGBuilder::visitIntrinsicCall(const CallInst &I, unsigned Intrinsic) {
(void)getControlRoot();
return 0;
}
+ case Intrinsic::clear_cache:
+ return TLI->getClearCacheBuiltinName();
case Intrinsic::donothing:
// ignore
return 0;
diff --git a/llvm/lib/Target/ARM/ARMISelLowering.h b/llvm/lib/Target/ARM/ARMISelLowering.h
index 022945f625a..5f6ea754348 100644
--- a/llvm/lib/Target/ARM/ARMISelLowering.h
+++ b/llvm/lib/Target/ARM/ARMISelLowering.h
@@ -384,6 +384,11 @@ namespace llvm {
bool shouldConvertConstantLoadToIntImm(const APInt &Imm,
Type *Ty) const override;
+ /// Clear cache library call
+ const char * getClearCacheBuiltinName() const {
+ return "__clear_cache";
+ }
+
protected:
std::pair<const TargetRegisterClass*, uint8_t>
findRepresentativeClass(MVT VT) const override;
diff --git a/llvm/lib/Target/Mips/MipsISelLowering.h b/llvm/lib/Target/Mips/MipsISelLowering.h
index 27492a8046c..b03cccfb586 100644
--- a/llvm/lib/Target/Mips/MipsISelLowering.h
+++ b/llvm/lib/Target/Mips/MipsISelLowering.h
@@ -583,6 +583,11 @@ namespace llvm {
bool MemcpyStrSrc,
MachineFunction &MF) const;
+ /// Clear cache library call
+ const char * getClearCacheBuiltinName() const {
+ return "__clear_cache";
+ }
+
/// isFPImmLegal - Returns true if the target can instruction select the
/// specified FP immediate natively. If false, the legalizer will
/// materialize the FP immediate as a load from a constant pool.
diff --git a/llvm/lib/Target/X86/X86ISelLowering.h b/llvm/lib/Target/X86/X86ISelLowering.h
index 894cfc6d0c1..ae13ca491cb 100644
--- a/llvm/lib/Target/X86/X86ISelLowering.h
+++ b/llvm/lib/Target/X86/X86ISelLowering.h
@@ -770,6 +770,11 @@ namespace llvm {
bool shouldConvertConstantLoadToIntImm(const APInt &Imm,
Type *Ty) const override;
+ /// Intel processors have a unified instruction and data cache
+ const char * getClearCacheBuiltinName() const {
+ return 0; // nothing to do, move along.
+ }
+
/// createFastISel - This method returns a target specific FastISel object,
/// or null if the target does not support "fast" ISel.
FastISel *createFastISel(FunctionLoweringInfo &funcInfo,
OpenPOWER on IntegriCloud