Starting to refactor Target to separate out code that's needed to fully describe

target machine from those that are only needed by codegen. The goal is to
sink the essential target description into MC layer so we can start building
MC based tools without needing to link in the entire codegen.

First step is to refactor TargetRegisterInfo. This patch added a base class
MCRegisterInfo which TargetRegisterInfo is derived from. Changed TableGen to
separate register description from the rest of the stuff.

llvm-svn: 133782

45 files changed, 189 insertions, 105 deletions

diff --git a/llvm/lib/CodeGen/RegisterClassInfo.h b/llvm/lib/CodeGen/RegisterClassInfo.h
index 6f7d9c94969..d21fd67efe8 100644
--- a/llvm/lib/CodeGen/RegisterClassInfo.h
+++ b/llvm/lib/CodeGen/RegisterClassInfo.h
@@ -112,7 +112,7 @@ public:
   /// register, so a register allocator needs to track its liveness and
   /// availability.
   bool isAllocatable(unsigned PhysReg) const {
-    return TRI->get(PhysReg).inAllocatableClass && !isReserved(PhysReg);
+    return TRI->isInAllocatableClass(PhysReg) && !isReserved(PhysReg);
   }
 };
 } // end namespace llvm
diff --git a/llvm/lib/Target/ARM/ARMBaseRegisterInfo.cpp b/llvm/lib/Target/ARM/ARMBaseRegisterInfo.cpp
index 9dc51b810ed..0e74ac0cf1c 100644
--- a/llvm/lib/Target/ARM/ARMBaseRegisterInfo.cpp
+++ b/llvm/lib/Target/ARM/ARMBaseRegisterInfo.cpp
@@ -39,6 +39,8 @@
 #include "llvm/ADT/BitVector.h"
 #include "llvm/ADT/SmallVector.h"
 #include "llvm/Support/CommandLine.h"
+#include "ARMGenRegisterDesc.inc"
+#include "ARMGenRegisterInfo.inc"
 
 using namespace llvm;
 
@@ -54,7 +56,8 @@ EnableBasePointer("arm-use-base-pointer", cl::Hidden, cl::init(true),
 
 ARMBaseRegisterInfo::ARMBaseRegisterInfo(const ARMBaseInstrInfo &tii,
                                          const ARMSubtarget &sti)
-  : ARMGenRegisterInfo(ARM::ADJCALLSTACKDOWN, ARM::ADJCALLSTACKUP),
+  : ARMGenRegisterInfo(ARMRegDesc, ARMRegInfoDesc,
+                       ARM::ADJCALLSTACKDOWN, ARM::ADJCALLSTACKUP),
     TII(tii), STI(sti),
     FramePtr((STI.isTargetDarwin() || STI.isThumb()) ? ARM::R7 : ARM::R11),
     BasePtr(ARM::R6) {
@@ -1287,5 +1290,3 @@ ARMBaseRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
       MI.setDesc(TII.get(ARM::t2SUBri));
   }
 }
-
-#include "ARMGenRegisterInfo.inc"
diff --git a/llvm/lib/Target/ARM/CMakeLists.txt b/llvm/lib/Target/ARM/CMakeLists.txt
index edc0054468e..6cb96895151 100644
--- a/llvm/lib/Target/ARM/CMakeLists.txt
+++ b/llvm/lib/Target/ARM/CMakeLists.txt
@@ -1,8 +1,9 @@
 set(LLVM_TARGET_DEFINITIONS ARM.td)
 
-tablegen(ARMGenRegisterInfo.h.inc -gen-register-desc-header)
 tablegen(ARMGenRegisterNames.inc -gen-register-enums)
-tablegen(ARMGenRegisterInfo.inc -gen-register-desc)
+tablegen(ARMGenRegisterDesc.inc -gen-register-desc)
+tablegen(ARMGenRegisterInfo.h.inc -gen-register-info-header)
+tablegen(ARMGenRegisterInfo.inc -gen-register-info)
 tablegen(ARMGenInstrNames.inc -gen-instr-enums)
 tablegen(ARMGenInstrInfo.inc -gen-instr-desc)
 tablegen(ARMGenCodeEmitter.inc -gen-emitter)
diff --git a/llvm/lib/Target/ARM/Makefile b/llvm/lib/Target/ARM/Makefile
index 65a6494986f..0a425143dce 100644
--- a/llvm/lib/Target/ARM/Makefile
+++ b/llvm/lib/Target/ARM/Makefile
@@ -12,9 +12,10 @@ LIBRARYNAME = LLVMARMCodeGen
 TARGET = ARM
 
 # Make sure that tblgen is run, first thing.
-BUILT_SOURCES = ARMGenRegisterInfo.h.inc ARMGenRegisterNames.inc \
-                ARMGenRegisterInfo.inc ARMGenInstrNames.inc \
-                ARMGenInstrInfo.inc ARMGenAsmWriter.inc ARMGenAsmMatcher.inc \
+BUILT_SOURCES = ARMGenRegisterNames.inc ARMGenRegisterDesc.inc \
+                ARMGenRegisterInfo.h.inc ARMGenRegisterInfo.inc \
+		ARMGenInstrNames.inc ARMGenInstrInfo.inc \
+		ARMGenAsmWriter.inc ARMGenAsmMatcher.inc \
                 ARMGenDAGISel.inc ARMGenSubtarget.inc \
                 ARMGenCodeEmitter.inc ARMGenCallingConv.inc \
                 ARMGenDecoderTables.inc ARMGenEDInfo.inc \
diff --git a/llvm/lib/Target/Alpha/AlphaRegisterInfo.cpp b/llvm/lib/Target/Alpha/AlphaRegisterInfo.cpp
index d6c3809960a..5ff846eca7a 100644
--- a/llvm/lib/Target/Alpha/AlphaRegisterInfo.cpp
+++ b/llvm/lib/Target/Alpha/AlphaRegisterInfo.cpp
@@ -33,10 +33,13 @@
 #include "llvm/ADT/BitVector.h"
 #include "llvm/ADT/STLExtras.h"
 #include <cstdlib>
+#include "AlphaGenRegisterDesc.inc"
+#include "AlphaGenRegisterInfo.inc"
 using namespace llvm;
 
 AlphaRegisterInfo::AlphaRegisterInfo(const TargetInstrInfo &tii)
-  : AlphaGenRegisterInfo(Alpha::ADJUSTSTACKDOWN, Alpha::ADJUSTSTACKUP),
+  : AlphaGenRegisterInfo(AlphaRegDesc, AlphaRegInfoDesc,
+                         Alpha::ADJUSTSTACKDOWN, Alpha::ADJUSTSTACKUP),
     TII(tii) {
 }
 
@@ -204,10 +207,8 @@ int AlphaRegisterInfo::getLLVMRegNum(unsigned DwarfRegNum, bool isEH) const {
   return -1;
 }
 
-#include "AlphaGenRegisterInfo.inc"
-
 std::string AlphaRegisterInfo::getPrettyName(unsigned reg)
 {
-  std::string s(RegisterDescriptors[reg].Name);
+  std::string s(AlphaRegDesc[reg].Name);
   return s;
 }
diff --git a/llvm/lib/Target/Alpha/CMakeLists.txt b/llvm/lib/Target/Alpha/CMakeLists.txt
index 454262ad631..1834b06653e 100644
--- a/llvm/lib/Target/Alpha/CMakeLists.txt
+++ b/llvm/lib/Target/Alpha/CMakeLists.txt
@@ -1,8 +1,9 @@
 set(LLVM_TARGET_DEFINITIONS Alpha.td)
 
-tablegen(AlphaGenRegisterInfo.h.inc -gen-register-desc-header)
 tablegen(AlphaGenRegisterNames.inc -gen-register-enums)
-tablegen(AlphaGenRegisterInfo.inc -gen-register-desc)
+tablegen(AlphaGenRegisterDesc.inc -gen-register-desc)
+tablegen(AlphaGenRegisterInfo.h.inc -gen-register-info-header)
+tablegen(AlphaGenRegisterInfo.inc -gen-register-info)
 tablegen(AlphaGenInstrNames.inc -gen-instr-enums)
 tablegen(AlphaGenInstrInfo.inc -gen-instr-desc)
 tablegen(AlphaGenAsmWriter.inc -gen-asm-writer)
diff --git a/llvm/lib/Target/Alpha/Makefile b/llvm/lib/Target/Alpha/Makefile
index 9564be680e5..f029793d083 100644
--- a/llvm/lib/Target/Alpha/Makefile
+++ b/llvm/lib/Target/Alpha/Makefile
@@ -12,9 +12,9 @@ LIBRARYNAME = LLVMAlphaCodeGen
 TARGET = Alpha
 
 # Make sure that tblgen is run, first thing.
-BUILT_SOURCES = AlphaGenRegisterInfo.h.inc AlphaGenRegisterNames.inc \
-                AlphaGenRegisterInfo.inc AlphaGenInstrNames.inc \
-                AlphaGenInstrInfo.inc \
+BUILT_SOURCES = AlphaGenRegisterNames.inc AlphaGenRegisterDesc.inc \
+                AlphaGenRegisterInfo.h.inc AlphaGenRegisterInfo.inc \
+		AlphaGenInstrNames.inc AlphaGenInstrInfo.inc \
                 AlphaGenAsmWriter.inc AlphaGenDAGISel.inc \
                 AlphaGenCallingConv.inc AlphaGenSubtarget.inc
 
diff --git a/llvm/lib/Target/Blackfin/BlackfinRegisterInfo.cpp b/llvm/lib/Target/Blackfin/BlackfinRegisterInfo.cpp
index 6ca460ef803..6377d8e4036 100644
--- a/llvm/lib/Target/Blackfin/BlackfinRegisterInfo.cpp
+++ b/llvm/lib/Target/Blackfin/BlackfinRegisterInfo.cpp
@@ -29,11 +29,14 @@
 #include "llvm/Type.h"
 #include "llvm/ADT/BitVector.h"
 #include "llvm/ADT/STLExtras.h"
+#include "BlackfinGenRegisterDesc.inc"
+#include "BlackfinGenRegisterInfo.inc"
 using namespace llvm;
 
 BlackfinRegisterInfo::BlackfinRegisterInfo(BlackfinSubtarget &st,
                                            const TargetInstrInfo &tii)
-  : BlackfinGenRegisterInfo(BF::ADJCALLSTACKDOWN, BF::ADJCALLSTACKUP),
+  : BlackfinGenRegisterInfo(BlackfinRegDesc, BlackfinRegInfoDesc,
+                            BF::ADJCALLSTACKDOWN, BF::ADJCALLSTACKUP),
     Subtarget(st),
     TII(tii) {}
 
@@ -356,6 +359,3 @@ int BlackfinRegisterInfo::getLLVMRegNum(unsigned DwarfRegNum,
   llvm_unreachable("What is the dwarf register number");
   return -1;
 }
-
-#include "BlackfinGenRegisterInfo.inc"
-
diff --git a/llvm/lib/Target/Blackfin/CMakeLists.txt b/llvm/lib/Target/Blackfin/CMakeLists.txt
index a47299ff161..10896c58648 100644
--- a/llvm/lib/Target/Blackfin/CMakeLists.txt
+++ b/llvm/lib/Target/Blackfin/CMakeLists.txt
@@ -1,8 +1,9 @@
 set(LLVM_TARGET_DEFINITIONS Blackfin.td)
 
-tablegen(BlackfinGenRegisterInfo.h.inc -gen-register-desc-header)
 tablegen(BlackfinGenRegisterNames.inc -gen-register-enums)
-tablegen(BlackfinGenRegisterInfo.inc -gen-register-desc)
+tablegen(BlackfinGenRegisterDesc.inc -gen-register-desc)
+tablegen(BlackfinGenRegisterInfo.h.inc -gen-register-info-header)
+tablegen(BlackfinGenRegisterInfo.inc -gen-register-info)
 tablegen(BlackfinGenInstrNames.inc -gen-instr-enums)
 tablegen(BlackfinGenInstrInfo.inc -gen-instr-desc)
 tablegen(BlackfinGenAsmWriter.inc -gen-asm-writer)
diff --git a/llvm/lib/Target/Blackfin/Makefile b/llvm/lib/Target/Blackfin/Makefile
index 5eb8e9a992b..8ea1dfb0676 100644
--- a/llvm/lib/Target/Blackfin/Makefile
+++ b/llvm/lib/Target/Blackfin/Makefile
@@ -12,8 +12,9 @@ LIBRARYNAME = LLVMBlackfinCodeGen
 TARGET = Blackfin
 
 # Make sure that tblgen is run, first thing.
-BUILT_SOURCES = BlackfinGenRegisterInfo.h.inc BlackfinGenRegisterNames.inc \
-                BlackfinGenRegisterInfo.inc BlackfinGenInstrNames.inc \
+BUILT_SOURCES = BlackfinGenRegisterNames.inc BlackfinGenRegisterDesc.inc \
+		BlackfinGenRegisterInfo.h.inc BlackfinGenRegisterInfo.inc \
+		BlackfinGenInstrNames.inc \
                 BlackfinGenInstrInfo.inc BlackfinGenAsmWriter.inc \
                 BlackfinGenDAGISel.inc BlackfinGenSubtarget.inc \
 		BlackfinGenCallingConv.inc BlackfinGenIntrinsics.inc
diff --git a/llvm/lib/Target/CellSPU/Makefile b/llvm/lib/Target/CellSPU/Makefile
index 77c66be9e85..de8a9476d14 100644
--- a/llvm/lib/Target/CellSPU/Makefile
+++ b/llvm/lib/Target/CellSPU/Makefile
@@ -10,8 +10,9 @@
 LEVEL = ../../..
 LIBRARYNAME = LLVMCellSPUCodeGen
 TARGET = SPU
-BUILT_SOURCES = SPUGenInstrNames.inc SPUGenRegisterNames.inc \
+BUILT_SOURCES = SPUGenInstrNames.inc \
 		SPUGenAsmWriter.inc SPUGenCodeEmitter.inc \
+		SPUGenRegisterNames.inc SPUGenRegisterDesc.inc \
 		SPUGenRegisterInfo.h.inc SPUGenRegisterInfo.inc \
 		SPUGenInstrInfo.inc SPUGenDAGISel.inc \
 		SPUGenSubtarget.inc SPUGenCallingConv.inc
diff --git a/llvm/lib/Target/CellSPU/SPURegisterInfo.cpp b/llvm/lib/Target/CellSPU/SPURegisterInfo.cpp
index 623ae76326b..34f3f9b1ad0 100644
--- a/llvm/lib/Target/CellSPU/SPURegisterInfo.cpp
+++ b/llvm/lib/Target/CellSPU/SPURegisterInfo.cpp
@@ -42,6 +42,8 @@
 #include "llvm/ADT/BitVector.h"
 #include "llvm/ADT/STLExtras.h"
 #include <cstdlib>
+#include "SPUGenRegisterDesc.inc"
+#include "SPUGenRegisterInfo.inc"
 
 using namespace llvm;
 
@@ -185,7 +187,8 @@ unsigned SPURegisterInfo::getRegisterNumbering(unsigned RegEnum) {
 
 SPURegisterInfo::SPURegisterInfo(const SPUSubtarget &subtarget,
                                  const TargetInstrInfo &tii) :
-  SPUGenRegisterInfo(SPU::ADJCALLSTACKDOWN, SPU::ADJCALLSTACKUP),
+  SPUGenRegisterInfo(SPURegDesc, SPURegInfoDesc,
+                     SPU::ADJCALLSTACKDOWN, SPU::ADJCALLSTACKUP),
   Subtarget(subtarget),
   TII(tii)
 {
@@ -371,5 +374,3 @@ SPURegisterInfo::findScratchRegister(MachineBasicBlock::iterator II,
   assert( Reg && "Register scavenger failed");
   return Reg;
 }
-
-#include "SPUGenRegisterInfo.inc"
diff --git a/llvm/lib/Target/MBlaze/CMakeLists.txt b/llvm/lib/Target/MBlaze/CMakeLists.txt
index 004057ad4ae..009564e9ab0 100644
--- a/llvm/lib/Target/MBlaze/CMakeLists.txt
+++ b/llvm/lib/Target/MBlaze/CMakeLists.txt
@@ -1,8 +1,9 @@
 set(LLVM_TARGET_DEFINITIONS MBlaze.td)
 
-tablegen(MBlazeGenRegisterInfo.h.inc -gen-register-desc-header)
 tablegen(MBlazeGenRegisterNames.inc -gen-register-enums)
-tablegen(MBlazeGenRegisterInfo.inc -gen-register-desc)
+tablegen(MBlazeGenRegisterDesc.inc -gen-register-desc)
+tablegen(MBlazeGenRegisterInfo.h.inc -gen-register-info-header)
+tablegen(MBlazeGenRegisterInfo.inc -gen-register-info)
 tablegen(MBlazeGenInstrNames.inc -gen-instr-enums)
 tablegen(MBlazeGenInstrInfo.inc -gen-instr-desc)
 tablegen(MBlazeGenCodeEmitter.inc -gen-emitter)
diff --git a/llvm/lib/Target/MBlaze/MBlazeRegisterInfo.cpp b/llvm/lib/Target/MBlaze/MBlazeRegisterInfo.cpp
index 517279fda51..f52c2e1a29a 100644
--- a/llvm/lib/Target/MBlaze/MBlazeRegisterInfo.cpp
+++ b/llvm/lib/Target/MBlaze/MBlazeRegisterInfo.cpp
@@ -36,12 +36,14 @@
 #include "llvm/Support/raw_ostream.h"
 #include "llvm/ADT/BitVector.h"
 #include "llvm/ADT/STLExtras.h"
-
+#include "MBlazeGenRegisterDesc.inc"
+#include "MBlazeGenRegisterInfo.inc"
 using namespace llvm;
 
 MBlazeRegisterInfo::
 MBlazeRegisterInfo(const MBlazeSubtarget &ST, const TargetInstrInfo &tii)
-  : MBlazeGenRegisterInfo(MBlaze::ADJCALLSTACKDOWN, MBlaze::ADJCALLSTACKUP),
+  : MBlazeGenRegisterInfo(MBlazeRegDesc, MBlazeRegInfoDesc,
+                          MBlaze::ADJCALLSTACKDOWN, MBlaze::ADJCALLSTACKUP),
     Subtarget(ST), TII(tii) {}
 
 /// getRegisterNumbering - Given the enum value for some register, e.g.
@@ -359,6 +361,3 @@ int MBlazeRegisterInfo::getDwarfRegNum(unsigned RegNo, bool isEH) const {
 int MBlazeRegisterInfo::getLLVMRegNum(unsigned DwarfRegNo, bool isEH) const {
   return MBlazeGenRegisterInfo::getLLVMRegNumFull(DwarfRegNo,0);
 }
-
-#include "MBlazeGenRegisterInfo.inc"
-
diff --git a/llvm/lib/Target/MBlaze/Makefile b/llvm/lib/Target/MBlaze/Makefile
index e01c60bb8c6..81fd5f7bba9 100644
--- a/llvm/lib/Target/MBlaze/Makefile
+++ b/llvm/lib/Target/MBlaze/Makefile
@@ -12,12 +12,13 @@ TARGET = MBlaze
 
 # Make sure that tblgen is run, first thing.
 BUILT_SOURCES = MBlazeGenRegisterInfo.h.inc MBlazeGenRegisterNames.inc \
-								MBlazeGenRegisterInfo.inc MBlazeGenInstrNames.inc \
-								MBlazeGenInstrInfo.inc MBlazeGenAsmWriter.inc \
-								MBlazeGenDAGISel.inc MBlazeGenAsmMatcher.inc \
-								MBlazeGenCodeEmitter.inc MBlazeGenCallingConv.inc \
-								MBlazeGenSubtarget.inc MBlazeGenIntrinsics.inc \
-								MBlazeGenEDInfo.inc
+                MBlazeGenRegisterInfo.inc MBlazeGenRegisterDesc.inc \
+                MBlazeGenInstrNames.inc \
+                MBlazeGenInstrInfo.inc MBlazeGenAsmWriter.inc \
+                MBlazeGenDAGISel.inc MBlazeGenAsmMatcher.inc \
+                MBlazeGenCodeEmitter.inc MBlazeGenCallingConv.inc \
+                MBlazeGenSubtarget.inc MBlazeGenIntrinsics.inc \
+                MBlazeGenEDInfo.inc
 
 DIRS = InstPrinter AsmParser Disassembler TargetInfo
 
diff --git a/llvm/lib/Target/MSP430/CMakeLists.txt b/llvm/lib/Target/MSP430/CMakeLists.txt
index 2c7cbb64418..90752fabdb6 100644
--- a/llvm/lib/Target/MSP430/CMakeLists.txt
+++ b/llvm/lib/Target/MSP430/CMakeLists.txt
@@ -1,8 +1,9 @@
 set(LLVM_TARGET_DEFINITIONS MSP430.td)
 
-tablegen(MSP430GenRegisterInfo.h.inc -gen-register-desc-header)
 tablegen(MSP430GenRegisterNames.inc -gen-register-enums)
-tablegen(MSP430GenRegisterInfo.inc -gen-register-desc)
+tablegen(MSP430GenRegisterDesc.inc -gen-register-desc)
+tablegen(MSP430GenRegisterInfo.h.inc -gen-register-info-header)
+tablegen(MSP430GenRegisterInfo.inc -gen-register-info)
 tablegen(MSP430GenInstrNames.inc -gen-instr-enums)
 tablegen(MSP430GenInstrInfo.inc -gen-instr-desc)
 tablegen(MSP430GenAsmWriter.inc -gen-asm-writer)
diff --git a/llvm/lib/Target/MSP430/MSP430RegisterInfo.cpp b/llvm/lib/Target/MSP430/MSP430RegisterInfo.cpp
index 53f4c2e4a88..397b7b403f7 100644
--- a/llvm/lib/Target/MSP430/MSP430RegisterInfo.cpp
+++ b/llvm/lib/Target/MSP430/MSP430RegisterInfo.cpp
@@ -25,13 +25,16 @@
 #include "llvm/Target/TargetOptions.h"
 #include "llvm/ADT/BitVector.h"
 #include "llvm/Support/ErrorHandling.h"
+#include "MSP430GenRegisterDesc.inc"
+#include "MSP430GenRegisterInfo.inc"
 
 using namespace llvm;
 
 // FIXME: Provide proper call frame setup / destroy opcodes.
 MSP430RegisterInfo::MSP430RegisterInfo(MSP430TargetMachine &tm,
                                        const TargetInstrInfo &tii)
-  : MSP430GenRegisterInfo(MSP430::ADJCALLSTACKDOWN, MSP430::ADJCALLSTACKUP),
+  : MSP430GenRegisterInfo(MSP430RegDesc, MSP430RegInfoDesc,
+                          MSP430::ADJCALLSTACKDOWN, MSP430::ADJCALLSTACKUP),
     TM(tm), TII(tii) {
   StackAlign = TM.getFrameLowering()->getStackAlignment();
 }
@@ -250,5 +253,3 @@ int MSP430RegisterInfo::getLLVMRegNum(unsigned RegNum, bool isEH) const {
   llvm_unreachable("Not implemented yet!");
   return 0;
 }
-
-#include "MSP430GenRegisterInfo.inc"
diff --git a/llvm/lib/Target/MSP430/Makefile b/llvm/lib/Target/MSP430/Makefile
index fa4e80b0ff3..8635646d5eb 100644
--- a/llvm/lib/Target/MSP430/Makefile
+++ b/llvm/lib/Target/MSP430/Makefile
@@ -13,7 +13,8 @@ TARGET = MSP430
 
 # Make sure that tblgen is run, first thing.
 BUILT_SOURCES = MSP430GenRegisterInfo.h.inc MSP430GenRegisterNames.inc \
-		MSP430GenRegisterInfo.inc MSP430GenInstrNames.inc \
+		MSP430GenRegisterInfo.inc MSP430GenRegisterDesc.inc \
+		MSP430GenInstrNames.inc \
 		MSP430GenInstrInfo.inc MSP430GenAsmWriter.inc \
 		MSP430GenDAGISel.inc MSP430GenCallingConv.inc \
 		MSP430GenSubtarget.inc
diff --git a/llvm/lib/Target/Mips/CMakeLists.txt b/llvm/lib/Target/Mips/CMakeLists.txt
index fd16516f385..f9d953639f4 100644
--- a/llvm/lib/Target/Mips/CMakeLists.txt
+++ b/llvm/lib/Target/Mips/CMakeLists.txt
@@ -1,8 +1,9 @@
 set(LLVM_TARGET_DEFINITIONS Mips.td)
 
-tablegen(MipsGenRegisterInfo.h.inc -gen-register-desc-header)
 tablegen(MipsGenRegisterNames.inc -gen-register-enums)
-tablegen(MipsGenRegisterInfo.inc -gen-register-desc)
+tablegen(MipsGenRegisterDesc.inc -gen-register-desc)
+tablegen(MipsGenRegisterInfo.h.inc -gen-register-info-header)
+tablegen(MipsGenRegisterInfo.inc -gen-register-info)
 tablegen(MipsGenInstrNames.inc -gen-instr-enums)
 tablegen(MipsGenInstrInfo.inc -gen-instr-desc)
 tablegen(MipsGenAsmWriter.inc -gen-asm-writer)
diff --git a/llvm/lib/Target/Mips/Makefile b/llvm/lib/Target/Mips/Makefile
index d16b066a624..d7eab61a72e 100644
--- a/llvm/lib/Target/Mips/Makefile
+++ b/llvm/lib/Target/Mips/Makefile
@@ -13,7 +13,8 @@ TARGET = Mips
 
 # Make sure that tblgen is run, first thing.
 BUILT_SOURCES = MipsGenRegisterInfo.h.inc MipsGenRegisterNames.inc \
-                MipsGenRegisterInfo.inc MipsGenInstrNames.inc \
+                MipsGenRegisterInfo.inc MipsGenRegisterDesc.inc \
+		MipsGenInstrNames.inc \
                 MipsGenInstrInfo.inc MipsGenAsmWriter.inc \
                 MipsGenDAGISel.inc MipsGenCallingConv.inc \
                 MipsGenSubtarget.inc
diff --git a/llvm/lib/Target/Mips/MipsRegisterInfo.cpp b/llvm/lib/Target/Mips/MipsRegisterInfo.cpp
index fa64f637c8e..6fdcf45e655 100644
--- a/llvm/lib/Target/Mips/MipsRegisterInfo.cpp
+++ b/llvm/lib/Target/Mips/MipsRegisterInfo.cpp
@@ -35,12 +35,15 @@
 #include "llvm/Support/raw_ostream.h"
 #include "llvm/ADT/BitVector.h"
 #include "llvm/ADT/STLExtras.h"
+#include "MipsGenRegisterDesc.inc"
+#include "MipsGenRegisterInfo.inc"
 
 using namespace llvm;
 
 MipsRegisterInfo::MipsRegisterInfo(const MipsSubtarget &ST,
                                    const TargetInstrInfo &tii)
-  : MipsGenRegisterInfo(Mips::ADJCALLSTACKDOWN, Mips::ADJCALLSTACKUP),
+  : MipsGenRegisterInfo(MipsRegDesc, MipsRegInfoDesc,
+                        Mips::ADJCALLSTACKDOWN, Mips::ADJCALLSTACKUP),
     Subtarget(ST), TII(tii) {}
 
 /// getRegisterNumbering - Given the enum value for some register, e.g.
@@ -285,5 +288,3 @@ getDwarfRegNum(unsigned RegNum, bool isEH) const {
 int MipsRegisterInfo::getLLVMRegNum(unsigned DwarfRegNo, bool isEH) const {
   return MipsGenRegisterInfo::getLLVMRegNumFull(DwarfRegNo,0);
 }
-
-#include "MipsGenRegisterInfo.inc"
diff --git a/llvm/lib/Target/PTX/CMakeLists.txt b/llvm/lib/Target/PTX/CMakeLists.txt
index c4448d6f0f5..540af72b7cf 100644
--- a/llvm/lib/Target/PTX/CMakeLists.txt
+++ b/llvm/lib/Target/PTX/CMakeLists.txt
@@ -5,8 +5,9 @@ tablegen(PTXGenCallingConv.inc -gen-callingconv)
 tablegen(PTXGenDAGISel.inc -gen-dag-isel)
 tablegen(PTXGenInstrInfo.inc -gen-instr-desc)
 tablegen(PTXGenInstrNames.inc -gen-instr-enums)
-tablegen(PTXGenRegisterInfo.inc -gen-register-desc)
-tablegen(PTXGenRegisterInfo.h.inc -gen-register-desc-header)
+tablegen(PTXGenRegisterDesc.inc -gen-register-desc)
+tablegen(PTXGenRegisterInfo.inc -gen-register-info)
+tablegen(PTXGenRegisterInfo.h.inc -gen-register-info-header)
 tablegen(PTXGenRegisterNames.inc -gen-register-enums)
 tablegen(PTXGenSubtarget.inc -gen-subtarget)
 
diff --git a/llvm/lib/Target/PTX/Makefile b/llvm/lib/Target/PTX/Makefile
index 844480f3b5a..1e471de3205 100644
--- a/llvm/lib/Target/PTX/Makefile
+++ b/llvm/lib/Target/PTX/Makefile
@@ -17,6 +17,7 @@ BUILT_SOURCES = PTXGenAsmWriter.inc \
 		PTXGenDAGISel.inc \
 		PTXGenInstrInfo.inc \
 		PTXGenInstrNames.inc \
+		PTXGenRegisterDesc.inc \
 		PTXGenRegisterInfo.inc \
 		PTXGenRegisterInfo.h.inc \
 		PTXGenRegisterNames.inc \
diff --git a/llvm/lib/Target/PTX/PTXRegisterInfo.cpp b/llvm/lib/Target/PTX/PTXRegisterInfo.cpp
index b7c7ee5d3ad..5673f963f70 100644
--- a/llvm/lib/Target/PTX/PTXRegisterInfo.cpp
+++ b/llvm/lib/Target/PTX/PTXRegisterInfo.cpp
@@ -19,9 +19,15 @@
 
 using namespace llvm;
 
+#include "PTXGenRegisterDesc.inc"
 #include "PTXGenRegisterInfo.inc"
 
 
+PTXRegisterInfo::PTXRegisterInfo(PTXTargetMachine &TM,
+                                 const TargetInstrInfo &TII)
+  : PTXGenRegisterInfo(PTXRegDesc, PTXRegInfoDesc) {
+}
+
 void PTXRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
                                           int SPAdj,
                                           RegScavenger *RS) const {
diff --git a/llvm/lib/Target/PTX/PTXRegisterInfo.h b/llvm/lib/Target/PTX/PTXRegisterInfo.h
index 223e965f2aa..67e8a1b0cfb 100644
--- a/llvm/lib/Target/PTX/PTXRegisterInfo.h
+++ b/llvm/lib/Target/PTX/PTXRegisterInfo.h
@@ -25,7 +25,7 @@ class MachineFunction;
 
 struct PTXRegisterInfo : public PTXGenRegisterInfo {
   PTXRegisterInfo(PTXTargetMachine &TM,
-                  const TargetInstrInfo &TII) {}
+                  const TargetInstrInfo &TII);
 
   virtual const unsigned
     *getCalleeSavedRegs(const MachineFunction *MF = 0) const {
diff --git a/llvm/lib/Target/PowerPC/CMakeLists.txt b/llvm/lib/Target/PowerPC/CMakeLists.txt
index f28257999d1..99caa9944bd 100644
--- a/llvm/lib/Target/PowerPC/CMakeLists.txt
+++ b/llvm/lib/Target/PowerPC/CMakeLists.txt
@@ -5,8 +5,9 @@ tablegen(PPCGenRegisterNames.inc -gen-register-enums)
 tablegen(PPCGenAsmWriter.inc -gen-asm-writer)
 tablegen(PPCGenCodeEmitter.inc -gen-emitter)
 tablegen(PPCGenMCCodeEmitter.inc -gen-emitter -mc-emitter)
-tablegen(PPCGenRegisterInfo.h.inc -gen-register-desc-header)
-tablegen(PPCGenRegisterInfo.inc -gen-register-desc)
+tablegen(PPCGenRegisterDesc.inc -gen-register-desc)
+tablegen(PPCGenRegisterInfo.h.inc -gen-register-info-header)
+tablegen(PPCGenRegisterInfo.inc -gen-register-info)
 tablegen(PPCGenInstrInfo.inc -gen-instr-desc)
 tablegen(PPCGenDAGISel.inc -gen-dag-isel)
 tablegen(PPCGenCallingConv.inc -gen-callingconv)
diff --git a/llvm/lib/Target/PowerPC/Makefile b/llvm/lib/Target/PowerPC/Makefile
index 030defe212c..3d01792bec7 100644
--- a/llvm/lib/Target/PowerPC/Makefile
+++ b/llvm/lib/Target/PowerPC/Makefile
@@ -14,6 +14,7 @@ TARGET = PPC
 # Make sure that tblgen is run, first thing.
 BUILT_SOURCES = PPCGenInstrNames.inc PPCGenRegisterNames.inc \
                 PPCGenAsmWriter.inc  PPCGenCodeEmitter.inc \
+		PPCGenRegisterDesc.inc \
                 PPCGenRegisterInfo.h.inc PPCGenRegisterInfo.inc \
                 PPCGenInstrInfo.inc PPCGenDAGISel.inc \
                 PPCGenSubtarget.inc PPCGenCallingConv.inc \
diff --git a/llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp b/llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
index fd62a88136c..3950517ca1b 100644
--- a/llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
+++ b/llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
@@ -43,6 +43,8 @@
 #include "llvm/ADT/BitVector.h"
 #include "llvm/ADT/STLExtras.h"
 #include <cstdlib>
+#include "PPCGenRegisterDesc.inc"
+#include "PPCGenRegisterInfo.inc"
 
 // FIXME (64-bit): Eventually enable by default.
 namespace llvm {
@@ -110,7 +112,8 @@ unsigned PPCRegisterInfo::getRegisterNumbering(unsigned RegEnum) {
 
 PPCRegisterInfo::PPCRegisterInfo(const PPCSubtarget &ST,
                                  const TargetInstrInfo &tii)
-  : PPCGenRegisterInfo(PPC::ADJCALLSTACKDOWN, PPC::ADJCALLSTACKUP),
+  : PPCGenRegisterInfo(PPCRegDesc, PPCRegInfoDesc,
+                       PPC::ADJCALLSTACKDOWN, PPC::ADJCALLSTACKUP),
     Subtarget(ST), TII(tii) {
   ImmToIdxMap[PPC::LD]   = PPC::LDX;    ImmToIdxMap[PPC::STD]  = PPC::STDX;
   ImmToIdxMap[PPC::LBZ]  = PPC::LBZX;   ImmToIdxMap[PPC::STB]  = PPC::STBX;
@@ -710,5 +713,3 @@ int PPCRegisterInfo::getLLVMRegNum(unsigned RegNum, bool isEH) const {
 
   return PPCGenRegisterInfo::getLLVMRegNumFull(RegNum, Flavour);
 }
-
-#include "PPCGenRegisterInfo.inc"
diff --git a/llvm/lib/Target/Sparc/CMakeLists.txt b/llvm/lib/Target/Sparc/CMakeLists.txt
index 6839234a470..243e8897236 100644
--- a/llvm/lib/Target/Sparc/CMakeLists.txt
+++ b/llvm/lib/Target/Sparc/CMakeLists.txt
@@ -1,8 +1,9 @@
 set(LLVM_TARGET_DEFINITIONS Sparc.td)
 
-tablegen(SparcGenRegisterInfo.h.inc -gen-register-desc-header)
 tablegen(SparcGenRegisterNames.inc -gen-register-enums)
-tablegen(SparcGenRegisterInfo.inc -gen-register-desc)
+tablegen(SparcGenRegisterDesc.inc -gen-register-desc)
+tablegen(SparcGenRegisterInfo.h.inc -gen-register-info-header)
+tablegen(SparcGenRegisterInfo.inc -gen-register-info)
 tablegen(SparcGenInstrNames.inc -gen-instr-enums)
 tablegen(SparcGenInstrInfo.inc -gen-instr-desc)
 tablegen(SparcGenAsmWriter.inc -gen-asm-writer)
diff --git a/llvm/lib/Target/Sparc/Makefile b/llvm/lib/Target/Sparc/Makefile
index 27942c56fb3..af7d9daa3d9 100644
--- a/llvm/lib/Target/Sparc/Makefile
+++ b/llvm/lib/Target/Sparc/Makefile
@@ -13,7 +13,8 @@ TARGET = Sparc
 
 # Make sure that tblgen is run, first thing.
 BUILT_SOURCES = SparcGenRegisterInfo.h.inc SparcGenRegisterNames.inc \
-                SparcGenRegisterInfo.inc SparcGenInstrNames.inc \
+                SparcGenRegisterInfo.inc SparcGenRegisterDesc.inc \
+		SparcGenInstrNames.inc \
                 SparcGenInstrInfo.inc SparcGenAsmWriter.inc \
                 SparcGenDAGISel.inc SparcGenSubtarget.inc SparcGenCallingConv.inc
 
diff --git a/llvm/lib/Target/Sparc/SparcRegisterInfo.cpp b/llvm/lib/Target/Sparc/SparcRegisterInfo.cpp
index 9fcf028fa60..c63f52e9589 100644
--- a/llvm/lib/Target/Sparc/SparcRegisterInfo.cpp
+++ b/llvm/lib/Target/Sparc/SparcRegisterInfo.cpp
@@ -23,11 +23,14 @@
 #include "llvm/Type.h"
 #include "llvm/ADT/BitVector.h"
 #include "llvm/ADT/STLExtras.h"
+#include "SparcGenRegisterDesc.inc"
+#include "SparcGenRegisterInfo.inc"
 using namespace llvm;
 
 SparcRegisterInfo::SparcRegisterInfo(SparcSubtarget &st,
                                      const TargetInstrInfo &tii)
-  : SparcGenRegisterInfo(SP::ADJCALLSTACKDOWN, SP::ADJCALLSTACKUP),
+  : SparcGenRegisterInfo(SparcRegDesc, SparcRegInfoDesc,
+                         SP::ADJCALLSTACKDOWN, SP::ADJCALLSTACKUP),
     Subtarget(st), TII(tii) {
 }
 
@@ -135,6 +138,3 @@ int SparcRegisterInfo::getDwarfRegNum(unsigned RegNum, bool isEH) const {
 int SparcRegisterInfo::getLLVMRegNum(unsigned DwarfRegNo, bool isEH) const {
   return SparcGenRegisterInfo::getLLVMRegNumFull(DwarfRegNo,0);
 }
-
-#include "SparcGenRegisterInfo.inc"
-
diff --git a/llvm/lib/Target/SystemZ/CMakeLists.txt b/llvm/lib/Target/SystemZ/CMakeLists.txt
index 1f5d3552ae7..3e06109a391 100644
--- a/llvm/lib/Target/SystemZ/CMakeLists.txt
+++ b/llvm/lib/Target/SystemZ/CMakeLists.txt
@@ -1,8 +1,9 @@
 set(LLVM_TARGET_DEFINITIONS SystemZ.td)
 
-tablegen(SystemZGenRegisterInfo.h.inc -gen-register-desc-header)
 tablegen(SystemZGenRegisterNames.inc -gen-register-enums)
-tablegen(SystemZGenRegisterInfo.inc -gen-register-desc)
+tablegen(SystemZGenRegisterDesc.inc -gen-register-desc)
+tablegen(SystemZGenRegisterInfo.h.inc -gen-register-info-header)
+tablegen(SystemZGenRegisterInfo.inc -gen-register-info)
 tablegen(SystemZGenInstrNames.inc -gen-instr-enums)
 tablegen(SystemZGenInstrInfo.inc -gen-instr-desc)
 tablegen(SystemZGenAsmWriter.inc -gen-asm-writer)
diff --git a/llvm/lib/Target/SystemZ/Makefile b/llvm/lib/Target/SystemZ/Makefile
index 6930e14c061..24817152fb0 100644
--- a/llvm/lib/Target/SystemZ/Makefile
+++ b/llvm/lib/Target/SystemZ/Makefile
@@ -13,7 +13,8 @@ TARGET = SystemZ
 
 # Make sure that tblgen is run, first thing.
 BUILT_SOURCES = SystemZGenRegisterInfo.h.inc SystemZGenRegisterNames.inc \
-                SystemZGenRegisterInfo.inc SystemZGenInstrNames.inc \
+                SystemZGenRegisterInfo.inc SystemZGenRegisterDesc.inc \
+		SystemZGenInstrNames.inc \
                 SystemZGenInstrInfo.inc SystemZGenAsmWriter.inc \
                 SystemZGenDAGISel.inc SystemZGenSubtarget.inc SystemZGenCallingConv.inc
 
diff --git a/llvm/lib/Target/SystemZ/SystemZRegisterInfo.cpp b/llvm/lib/Target/SystemZ/SystemZRegisterInfo.cpp
index d5c165f640e..a587e1c2895 100644
--- a/llvm/lib/Target/SystemZ/SystemZRegisterInfo.cpp
+++ b/llvm/lib/Target/SystemZ/SystemZRegisterInfo.cpp
@@ -25,11 +25,14 @@
 #include "llvm/Target/TargetMachine.h"
 #include "llvm/Target/TargetOptions.h"
 #include "llvm/ADT/BitVector.h"
+#include "SystemZGenRegisterDesc.inc"
+#include "SystemZGenRegisterInfo.inc"
 using namespace llvm;
 
 SystemZRegisterInfo::SystemZRegisterInfo(SystemZTargetMachine &tm,
                                          const SystemZInstrInfo &tii)
-  : SystemZGenRegisterInfo(SystemZ::ADJCALLSTACKUP, SystemZ::ADJCALLSTACKDOWN),
+  : SystemZGenRegisterInfo(SystemZRegDesc, SystemZRegInfoDesc,
+                           SystemZ::ADJCALLSTACKUP, SystemZ::ADJCALLSTACKDOWN),
     TM(tm), TII(tii) {
 }
 
@@ -153,6 +156,3 @@ int SystemZRegisterInfo::getLLVMRegNum(unsigned DwarfRegNo, bool isEH) const {
   assert(0 && "What is the dwarf register number");
   return -1;
 }
-
-
-#include "SystemZGenRegisterInfo.inc"
diff --git a/llvm/lib/Target/TargetRegisterInfo.cpp b/llvm/lib/Target/TargetRegisterInfo.cpp
index bae3343a850..d01130a5ae4 100644
--- a/llvm/lib/Target/TargetRegisterInfo.cpp
+++ b/llvm/lib/Target/TargetRegisterInfo.cpp
@@ -20,15 +20,12 @@
 
 using namespace llvm;
 
-TargetRegisterInfo::TargetRegisterInfo(const TargetRegisterDesc *D, unsigned NR,
+TargetRegisterInfo::TargetRegisterInfo(const TargetRegisterInfoDesc *ID,
                              regclass_iterator RCB, regclass_iterator RCE,
                              const char *const *subregindexnames,
                              int CFSO, int CFDO)
-  : Desc(D), SubRegIndexNames(subregindexnames), NumRegs(NR),
+  : InfoDesc(ID), SubRegIndexNames(subregindexnames),
     RegClassBegin(RCB), RegClassEnd(RCE) {
-  assert(isPhysicalRegister(NumRegs) &&
-         "Target has too many physical registers!");
-
   CallFrameSetupOpcode   = CFSO;
   CallFrameDestroyOpcode = CFDO;
 }
@@ -86,7 +83,7 @@ static void getAllocatableSetForRC(const MachineFunction &MF,
 
 BitVector TargetRegisterInfo::getAllocatableSet(const MachineFunction &MF,
                                           const TargetRegisterClass *RC) const {
-  BitVector Allocatable(NumRegs);
+  BitVector Allocatable(getNumRegs());
   if (RC) {
     getAllocatableSetForRC(MF, RC, Allocatable);
   } else {
diff --git a/llvm/lib/Target/X86/CMakeLists.txt b/llvm/lib/Target/X86/CMakeLists.txt
index b5fa94f12bc..5e0c84fcab5 100644
--- a/llvm/lib/Target/X86/CMakeLists.txt
+++ b/llvm/lib/Target/X86/CMakeLists.txt
@@ -1,8 +1,9 @@
 set(LLVM_TARGET_DEFINITIONS X86.td)
 
-tablegen(X86GenRegisterInfo.h.inc -gen-register-desc-header)
 tablegen(X86GenRegisterNames.inc -gen-register-enums)
-tablegen(X86GenRegisterInfo.inc -gen-register-desc)
+tablegen(X86GenRegisterDesc.inc -gen-register-desc)
+tablegen(X86GenRegisterInfo.h.inc -gen-register-info-header)
+tablegen(X86GenRegisterInfo.inc -gen-register-info)
 tablegen(X86GenDisassemblerTables.inc -gen-disassembler)
 tablegen(X86GenInstrNames.inc -gen-instr-enums)
 tablegen(X86GenInstrInfo.inc -gen-instr-desc)
diff --git a/llvm/lib/Target/X86/Makefile b/llvm/lib/Target/X86/Makefile
index 12fb090d4dc..9cd17eed6c5 100644
--- a/llvm/lib/Target/X86/Makefile
+++ b/llvm/lib/Target/X86/Makefile
@@ -12,14 +12,15 @@ LIBRARYNAME = LLVMX86CodeGen
 TARGET = X86
 
 # Make sure that tblgen is run, first thing.
-BUILT_SOURCES = X86GenRegisterInfo.h.inc X86GenRegisterNames.inc \
-                X86GenRegisterInfo.inc X86GenInstrNames.inc \
-                X86GenInstrInfo.inc X86GenAsmWriter.inc X86GenAsmMatcher.inc \
+BUILT_SOURCES = X86GenRegisterNames.inc X86GenRegisterDesc.inc \
+		X86GenRegisterInfo.h.inc X86GenRegisterInfo.inc \
+		X86GenInstrNames.inc X86GenInstrInfo.inc \
+		X86GenAsmWriter.inc X86GenAsmMatcher.inc \
                 X86GenAsmWriter1.inc X86GenDAGISel.inc  \
                 X86GenDisassemblerTables.inc X86GenFastISel.inc \
                 X86GenCallingConv.inc X86GenSubtarget.inc \
 		X86GenEDInfo.inc
 
-DIRS = InstPrinter AsmParser Disassembler TargetInfo Utils
+DIRS = InstPrinter AsmParser Disassembler TargetInfo TargetDesc Utils
 
 include $(LEVEL)/Makefile.common
diff --git a/llvm/lib/Target/X86/TargetDesc/Makefile b/llvm/lib/Target/X86/TargetDesc/Makefile
new file mode 100644
index 00000000000..b19774ee379
--- /dev/null
+++ b/llvm/lib/Target/X86/TargetDesc/Makefile
@@ -0,0 +1,16 @@
+##===- lib/Target/X86/TargetDesc/Makefile ------------------*- Makefile -*-===##
+#
+#                     The LLVM Compiler Infrastructure
+#
+# This file is distributed under the University of Illinois Open Source
+# License. See LICENSE.TXT for details.
+#
+##===----------------------------------------------------------------------===##
+
+LEVEL = ../../../..
+LIBRARYNAME = LLVMX86Desc
+
+# Hack: we need to include 'main' target directory to grab private headers
+CPP.Flags += -I$(PROJ_OBJ_DIR)/.. -I$(PROJ_SRC_DIR)/..
+
+include $(LEVEL)/Makefile.common
diff --git a/llvm/lib/Target/X86/TargetDesc/X86TargetDesc.cpp b/llvm/lib/Target/X86/TargetDesc/X86TargetDesc.cpp
new file mode 100644
index 00000000000..cf03d48f3c4
--- /dev/null
+++ b/llvm/lib/Target/X86/TargetDesc/X86TargetDesc.cpp
@@ -0,0 +1,23 @@
+//===-- X86TargetDesc.cpp - X86 Target Descriptions -------------*- C++ -*-===//
+//
+//                     The LLVM Compiler Infrastructure
+//
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
+//
+//===----------------------------------------------------------------------===//
+//
+// This file provides X86 specific target descriptions.
+//
+//===----------------------------------------------------------------------===//
+
+#include "X86TargetDesc.h"
+#include "llvm/MC/MCRegisterInfo.h"
+#include "X86GenRegisterDesc.inc"
+using namespace llvm;
+
+MCRegisterInfo *createX86MCRegisterInfo() {
+  MCRegisterInfo *X = new MCRegisterInfo();
+  InitX86MCRegisterInfo(X);
+  return X;
+}
diff --git a/llvm/lib/Target/X86/TargetDesc/X86TargetDesc.h b/llvm/lib/Target/X86/TargetDesc/X86TargetDesc.h
new file mode 100644
index 00000000000..d08aec773ba
--- /dev/null
+++ b/llvm/lib/Target/X86/TargetDesc/X86TargetDesc.h
@@ -0,0 +1,17 @@
+//===-- X86TargetDesc.h - X86 Target Descriptions ---------------*- C++ -*-===//
+//
+//                     The LLVM Compiler Infrastructure
+//
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
+//
+//===----------------------------------------------------------------------===//
+//
+// This file provides X86 specific target descriptions.
+//
+//===----------------------------------------------------------------------===//
+
+// Defines symbolic names for X86 registers.  This defines a mapping from
+// register name to register number.
+//
+#include "X86GenRegisterNames.inc"
diff --git a/llvm/lib/Target/X86/X86.h b/llvm/lib/Target/X86/X86.h
index 0ca43669004..ec78d489a63 100644
--- a/llvm/lib/Target/X86/X86.h
+++ b/llvm/lib/Target/X86/X86.h
@@ -88,10 +88,7 @@ extern Target TheX86_32Target, TheX86_64Target;
 
 } // End llvm namespace
 
-// Defines symbolic names for X86 registers.  This defines a mapping from
-// register name to register number.
-//
-#include "X86GenRegisterNames.inc"
+#include "TargetDesc/X86TargetDesc.h"
 
 // Defines symbolic names for the X86 instructions.
 //
diff --git a/llvm/lib/Target/X86/X86RegisterInfo.cpp b/llvm/lib/Target/X86/X86RegisterInfo.cpp
index fa3e3f8429c..c67da211072 100644
--- a/llvm/lib/Target/X86/X86RegisterInfo.cpp
+++ b/llvm/lib/Target/X86/X86RegisterInfo.cpp
@@ -39,6 +39,8 @@
 #include "llvm/ADT/STLExtras.h"
 #include "llvm/Support/ErrorHandling.h"
 #include "llvm/Support/CommandLine.h"
+#include "X86GenRegisterDesc.inc"
+#include "X86GenRegisterInfo.inc"
 using namespace llvm;
 
 cl::opt<bool>
@@ -49,7 +51,8 @@ ForceStackAlign("force-align-stack",
 
 X86RegisterInfo::X86RegisterInfo(X86TargetMachine &tm,
                                  const TargetInstrInfo &tii)
-  : X86GenRegisterInfo(tm.getSubtarget<X86Subtarget>().is64Bit() ?
+  : X86GenRegisterInfo(X86RegDesc, X86RegInfoDesc,
+                       tm.getSubtarget<X86Subtarget>().is64Bit() ?
                          X86::ADJCALLSTACKDOWN64 :
                          X86::ADJCALLSTACKDOWN32,
                        tm.getSubtarget<X86Subtarget>().is64Bit() ?
@@ -918,8 +921,6 @@ unsigned getX86SubSuperRegister(unsigned Reg, EVT VT, bool High) {
 }
 }
 
-#include "X86GenRegisterInfo.inc"
-
 namespace {
   struct MSAH : public MachineFunctionPass {
     static char ID;
diff --git a/llvm/lib/Target/XCore/CMakeLists.txt b/llvm/lib/Target/XCore/CMakeLists.txt
index 9093de69158..1ed1538b20f 100644
--- a/llvm/lib/Target/XCore/CMakeLists.txt
+++ b/llvm/lib/Target/XCore/CMakeLists.txt
@@ -1,8 +1,8 @@
 set(LLVM_TARGET_DEFINITIONS XCore.td)
 
-tablegen(XCoreGenRegisterInfo.h.inc -gen-register-desc-header)
-tablegen(XCoreGenRegisterNames.inc -gen-register-enums)
-tablegen(XCoreGenRegisterInfo.inc -gen-register-desc)
+tablegen(XCoreGenRegisterDesc.inc -gen-register-desc)
+tablegen(XCoreGenRegisterInfo.h.inc -gen-register-info-header)
+tablegen(XCoreGenRegisterInfo.inc -gen-register-info)
 tablegen(XCoreGenInstrNames.inc -gen-instr-enums)
 tablegen(XCoreGenInstrInfo.inc -gen-instr-desc)
 tablegen(XCoreGenAsmWriter.inc -gen-asm-writer)
diff --git a/llvm/lib/Target/XCore/Makefile b/llvm/lib/Target/XCore/Makefile
index 6c1ef886031..f67ef517a17 100644
--- a/llvm/lib/Target/XCore/Makefile
+++ b/llvm/lib/Target/XCore/Makefile
@@ -13,7 +13,8 @@ TARGET = XCore
 
 # Make sure that tblgen is run, first thing.
 BUILT_SOURCES = XCoreGenRegisterInfo.h.inc XCoreGenRegisterNames.inc \
-                XCoreGenRegisterInfo.inc XCoreGenInstrNames.inc \
+                XCoreGenRegisterInfo.inc XCoreGenRegisterDesc.inc \
+		XCoreGenInstrNames.inc \
                 XCoreGenInstrInfo.inc XCoreGenAsmWriter.inc \
                 XCoreGenDAGISel.inc XCoreGenCallingConv.inc \
 		XCoreGenSubtarget.inc
diff --git a/llvm/lib/Target/XCore/XCoreRegisterInfo.cpp b/llvm/lib/Target/XCore/XCoreRegisterInfo.cpp
index 46c9e57c1af..966e33b6db7 100644
--- a/llvm/lib/Target/XCore/XCoreRegisterInfo.cpp
+++ b/llvm/lib/Target/XCore/XCoreRegisterInfo.cpp
@@ -32,11 +32,13 @@
 #include "llvm/Support/Debug.h"
 #include "llvm/Support/ErrorHandling.h"
 #include "llvm/Support/raw_ostream.h"
-
+#include "XCoreGenRegisterDesc.inc"
+#include "XCoreGenRegisterInfo.inc"
 using namespace llvm;
 
 XCoreRegisterInfo::XCoreRegisterInfo(const TargetInstrInfo &tii)
-  : XCoreGenRegisterInfo(XCore::ADJCALLSTACKDOWN, XCore::ADJCALLSTACKUP),
+  : XCoreGenRegisterInfo(XCoreRegDesc, XCoreRegInfoDesc,
+                         XCore::ADJCALLSTACKDOWN, XCore::ADJCALLSTACKUP),
     TII(tii) {
 }
 
@@ -328,6 +330,3 @@ unsigned XCoreRegisterInfo::getFrameRegister(const MachineFunction &MF) const {
 unsigned XCoreRegisterInfo::getRARegister() const {
   return XCore::LR;
 }
-
-#include "XCoreGenRegisterInfo.inc"
-