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authorAhmed Bougacha <ahmed.bougacha@gmail.com>2016-08-02 16:17:10 +0000
committerAhmed Bougacha <ahmed.bougacha@gmail.com>2016-08-02 16:17:10 +0000
commit24712655080209457ce6f82a5526c2611c7d690e (patch)
tree6c553f5e6ae2c1a32a3e7169fce833f0d066d9de /llvm/lib
parent18d88983179a300adcae41c835fbcf7990c91b2d (diff)
downloadbcm5719-llvm-24712655080209457ce6f82a5526c2611c7d690e.tar.gz
bcm5719-llvm-24712655080209457ce6f82a5526c2611c7d690e.zip
[GlobalISel] Add RegBankSelected MachineFunction property.
RegBankSelected: the RegBankSelect pass ran and all generic virtual registers have been assigned to a register bank. This lets us enforce certain invariants across passes. This property is GlobalISel-specific, but is always available. llvm-svn: 277475
Diffstat (limited to 'llvm/lib')
-rw-r--r--llvm/lib/CodeGen/MIRParser/MIRParser.cpp3
-rw-r--r--llvm/lib/CodeGen/MIRPrinter.cpp2
-rw-r--r--llvm/lib/CodeGen/MachineFunction.cpp3
3 files changed, 8 insertions, 0 deletions
diff --git a/llvm/lib/CodeGen/MIRParser/MIRParser.cpp b/llvm/lib/CodeGen/MIRParser/MIRParser.cpp
index 035b0ae5246..fcec6deb100 100644
--- a/llvm/lib/CodeGen/MIRParser/MIRParser.cpp
+++ b/llvm/lib/CodeGen/MIRParser/MIRParser.cpp
@@ -295,6 +295,9 @@ bool MIRParserImpl::initializeMachineFunction(MachineFunction &MF) {
if (YamlMF.Legalized)
MF.getProperties().set(MachineFunctionProperties::Property::Legalized);
+ if (YamlMF.RegBankSelected)
+ MF.getProperties().set(
+ MachineFunctionProperties::Property::RegBankSelected);
PerFunctionMIParsingState PFS(MF, SM, IRSlots);
if (initializeRegisterInfo(PFS, YamlMF))
diff --git a/llvm/lib/CodeGen/MIRPrinter.cpp b/llvm/lib/CodeGen/MIRPrinter.cpp
index fdd7a42ac62..d08feec0046 100644
--- a/llvm/lib/CodeGen/MIRPrinter.cpp
+++ b/llvm/lib/CodeGen/MIRPrinter.cpp
@@ -180,6 +180,8 @@ void MIRPrinter::print(const MachineFunction &MF) {
YamlMF.Legalized = MF.getProperties().hasProperty(
MachineFunctionProperties::Property::Legalized);
+ YamlMF.RegBankSelected = MF.getProperties().hasProperty(
+ MachineFunctionProperties::Property::RegBankSelected);
convert(YamlMF, MF.getRegInfo(), MF.getSubtarget().getRegisterInfo());
ModuleSlotTracker MST(MF.getFunction()->getParent());
diff --git a/llvm/lib/CodeGen/MachineFunction.cpp b/llvm/lib/CodeGen/MachineFunction.cpp
index 202cf3cdf03..6cd3b65b294 100644
--- a/llvm/lib/CodeGen/MachineFunction.cpp
+++ b/llvm/lib/CodeGen/MachineFunction.cpp
@@ -79,6 +79,9 @@ void MachineFunctionProperties::print(raw_ostream &ROS, bool OnlySet) const {
case Property::Legalized:
ROS << (HasProperty ? "" : "not ") << "legalized";
break;
+ case Property::RegBankSelected:
+ ROS << (HasProperty ? "" : "not ") << "RegBank-selected";
+ break;
default:
break;
}
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