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| author | David Goodwin <david_goodwin@apple.com> | 2009-10-01 22:19:57 +0000 |
|---|---|---|
| committer | David Goodwin <david_goodwin@apple.com> | 2009-10-01 22:19:57 +0000 |
| commit | 1cc6dd97dac3da3605aa5e71362f24e9a6c10db5 (patch) | |
| tree | 1dde36065d9ccc44394dde8f5694bf7e7eb67b5b /llvm/lib | |
| parent | a0f91ad59c4be3bc6425d74da768e51a603c43a9 (diff) | |
| download | bcm5719-llvm-1cc6dd97dac3da3605aa5e71362f24e9a6c10db5.tar.gz bcm5719-llvm-1cc6dd97dac3da3605aa5e71362f24e9a6c10db5.zip | |
Remove neonfp attribute and instead set default based on CPU string. Add -arm-use-neon-fp to override the default.
llvm-svn: 83218
Diffstat (limited to 'llvm/lib')
| -rw-r--r-- | llvm/lib/CodeGen/PostRASchedulerList.cpp | 2 | ||||
| -rw-r--r-- | llvm/lib/Target/ARM/ARM.td | 5 | ||||
| -rw-r--r-- | llvm/lib/Target/ARM/ARMSubtarget.cpp | 8 |
3 files changed, 9 insertions, 6 deletions
diff --git a/llvm/lib/CodeGen/PostRASchedulerList.cpp b/llvm/lib/CodeGen/PostRASchedulerList.cpp index eddc4890306..2dafa87cf30 100644 --- a/llvm/lib/CodeGen/PostRASchedulerList.cpp +++ b/llvm/lib/CodeGen/PostRASchedulerList.cpp @@ -54,7 +54,7 @@ STATISTIC(NumStalls, "Number of pipeline stalls"); static cl::opt<bool> EnablePostRAScheduler("post-RA-scheduler", cl::desc("Enable scheduling after register allocation"), - cl::init(false)); + cl::init(false), cl::Hidden); static cl::opt<bool> EnableAntiDepBreaking("break-anti-dependencies", cl::desc("Break post-RA scheduling anti-dependencies"), diff --git a/llvm/lib/Target/ARM/ARM.td b/llvm/lib/Target/ARM/ARM.td index 8069e2b6a85..8851fbbf248 100644 --- a/llvm/lib/Target/ARM/ARM.td +++ b/llvm/lib/Target/ARM/ARM.td @@ -40,9 +40,6 @@ def FeatureNEON : SubtargetFeature<"neon", "ARMFPUType", "NEON", "Enable NEON instructions">; def FeatureThumb2 : SubtargetFeature<"thumb2", "ThumbMode", "Thumb2", "Enable Thumb2 instructions">; -def FeatureNEONFP : SubtargetFeature<"neonfp", "UseNEONForSinglePrecisionFP", - "true", - "Use NEON for single-precision FP">; //===----------------------------------------------------------------------===// // ARM Processors supported. @@ -105,7 +102,7 @@ def : ProcNoItin<"arm1156t2f-s", [ArchV6T2, FeatureThumb2, FeatureVFP2]>; // V7 Processors. def : Processor<"cortex-a8", CortexA8Itineraries, - [ArchV7A, FeatureThumb2, FeatureNEON, FeatureNEONFP]>; + [ArchV7A, FeatureThumb2, FeatureNEON]>; def : ProcNoItin<"cortex-a9", [ArchV7A, FeatureThumb2, FeatureNEON]>; //===----------------------------------------------------------------------===// diff --git a/llvm/lib/Target/ARM/ARMSubtarget.cpp b/llvm/lib/Target/ARM/ARMSubtarget.cpp index 704cf7abfb3..cf1ee3f0295 100644 --- a/llvm/lib/Target/ARM/ARMSubtarget.cpp +++ b/llvm/lib/Target/ARM/ARMSubtarget.cpp @@ -21,12 +21,16 @@ using namespace llvm; static cl::opt<bool> ReserveR9("arm-reserve-r9", cl::Hidden, cl::desc("Reserve R9, making it unavailable as GPR")); +static cl::opt<bool> +UseNEONFP("arm-use-neon-fp", + cl::desc("Use NEON for single-precision FP"), + cl::init(false), cl::Hidden); ARMSubtarget::ARMSubtarget(const std::string &TT, const std::string &FS, bool isThumb) : ARMArchVersion(V4T) , ARMFPUType(None) - , UseNEONForSinglePrecisionFP(false) + , UseNEONForSinglePrecisionFP(UseNEONFP) , IsThumb(isThumb) , ThumbMode(Thumb1) , PostRAScheduler(false) @@ -97,6 +101,8 @@ ARMSubtarget::ARMSubtarget(const std::string &TT, const std::string &FS, // Set CPU specific features. if (CPUString == "cortex-a8") { PostRAScheduler = true; + if (UseNEONFP.getPosition() == 0) + UseNEONForSinglePrecisionFP = true; } } |
