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| author | Matt Arsenault <Matthew.Arsenault@amd.com> | 2018-12-21 03:14:45 +0000 |
|---|---|---|
| committer | Matt Arsenault <Matthew.Arsenault@amd.com> | 2018-12-21 03:14:45 +0000 |
| commit | f4c21c575af1d552bf68c39a0b554b6235f48c6c (patch) | |
| tree | c3a82be70b5e3da5eca367ee8e6b0cc9ca8bd817 /llvm/lib/Target | |
| parent | d16b7722786b6ee7b0505653cbcaac0aab16dfb7 (diff) | |
| download | bcm5719-llvm-f4c21c575af1d552bf68c39a0b554b6235f48c6c.tar.gz bcm5719-llvm-f4c21c575af1d552bf68c39a0b554b6235f48c6c.zip | |
AMDGPU/GlobalISel: RegBankSelect for some fp ops
llvm-svn: 349880
Diffstat (limited to 'llvm/lib/Target')
| -rw-r--r-- | llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp | 7 | ||||
| -rw-r--r-- | llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp | 4 |
2 files changed, 11 insertions, 0 deletions
diff --git a/llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp b/llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp index c7df4440749..9a27401fa4a 100644 --- a/llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp +++ b/llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp @@ -161,6 +161,13 @@ AMDGPULegalizerInfo::AMDGPULegalizerInfo(const GCNSubtarget &ST, setAction({G_FPTOUI, S32}, Legal); setAction({G_FPTOUI, 1, S32}, Legal); + setAction({G_FPOW, S32}, Legal); + setAction({G_FEXP2, S32}, Legal); + setAction({G_FLOG2, S32}, Legal); + + getActionDefinitionsBuilder({G_INTRINSIC_TRUNC, G_INTRINSIC_ROUND}) + .legalFor({S32, S64}); + for (LLT PtrTy : AddrSpaces) { LLT IdxTy = LLT::scalar(PtrTy.getSizeInBits()); setAction({G_GEP, PtrTy}, Legal); diff --git a/llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp b/llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp index 395bdd79a2c..7da4c32a632 100644 --- a/llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp +++ b/llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp @@ -388,6 +388,10 @@ AMDGPURegisterBankInfo::getInstrMapping(const MachineInstr &MI) const { case AMDGPU::G_SITOFP: case AMDGPU::G_UITOFP: case AMDGPU::G_FPTRUNC: + case AMDGPU::G_FEXP2: + case AMDGPU::G_FLOG2: + case AMDGPU::G_INTRINSIC_TRUNC: + case AMDGPU::G_INTRINSIC_ROUND: return getDefaultMappingVOP(MI); case AMDGPU::G_IMPLICIT_DEF: { unsigned Size = MRI.getType(MI.getOperand(0).getReg()).getSizeInBits(); |
