[X86] Add 'Z' to the internal names of various EVEX instructions for overall consistency.

llvm-svn: 334785

3 files changed, 76 insertions, 76 deletions

diff --git a/llvm/lib/Target/X86/X86EvexToVex.cpp b/llvm/lib/Target/X86/X86EvexToVex.cpp
index c1d8086e9d9..b158042a857 100644
--- a/llvm/lib/Target/X86/X86EvexToVex.cpp
+++ b/llvm/lib/Target/X86/X86EvexToVex.cpp
@@ -205,14 +205,14 @@ static bool performCustomAdjustments(MachineInstr &MI, unsigned NewOpc) {
   case X86::VRNDSCALEPDZ256rmi:
   case X86::VRNDSCALEPSZ256rri:
   case X86::VRNDSCALEPSZ256rmi:
-  case X86::VRNDSCALESDr:
-  case X86::VRNDSCALESDm:
-  case X86::VRNDSCALESSr:
-  case X86::VRNDSCALESSm:
-  case X86::VRNDSCALESDr_Int:
-  case X86::VRNDSCALESDm_Int:
-  case X86::VRNDSCALESSr_Int:
-  case X86::VRNDSCALESSm_Int:
+  case X86::VRNDSCALESDZr:
+  case X86::VRNDSCALESDZm:
+  case X86::VRNDSCALESSZr:
+  case X86::VRNDSCALESSZm:
+  case X86::VRNDSCALESDZr_Int:
+  case X86::VRNDSCALESDZm_Int:
+  case X86::VRNDSCALESSZr_Int:
+  case X86::VRNDSCALESSZm_Int:
     const MachineOperand &Imm = MI.getOperand(MI.getNumExplicitOperands()-1);
     int64_t ImmVal = Imm.getImm();
     // Ensure that only bits 3:0 of the immediate are used.
diff --git a/llvm/lib/Target/X86/X86InstrAVX512.td b/llvm/lib/Target/X86/X86InstrAVX512.td
index fc9c05ecf37..d0ef7cc975f 100644
--- a/llvm/lib/Target/X86/X86InstrAVX512.td
+++ b/llvm/lib/Target/X86/X86InstrAVX512.td
@@ -8292,18 +8292,18 @@ multiclass avx512_fp14_s<bits<8> opc, string OpcodeStr, SDNode OpNode,
 }
 }
 
-defm VRCP14SS : avx512_fp14_s<0x4D, "vrcp14ss", X86rcp14s, SchedWriteFRcp.Scl,
-                              f32x_info>, EVEX_CD8<32, CD8VT1>,
-                              T8PD;
-defm VRCP14SD : avx512_fp14_s<0x4D, "vrcp14sd", X86rcp14s, SchedWriteFRcp.Scl,
-                              f64x_info>, VEX_W, EVEX_CD8<64, CD8VT1>,
-                              T8PD;
-defm VRSQRT14SS : avx512_fp14_s<0x4F, "vrsqrt14ss", X86rsqrt14s,
-                                SchedWriteFRsqrt.Scl, f32x_info>,
-                                EVEX_CD8<32, CD8VT1>, T8PD;
-defm VRSQRT14SD : avx512_fp14_s<0x4F, "vrsqrt14sd", X86rsqrt14s,
-                                SchedWriteFRsqrt.Scl, f64x_info>, VEX_W,
-                                EVEX_CD8<64, CD8VT1>, T8PD;
+defm VRCP14SSZ : avx512_fp14_s<0x4D, "vrcp14ss", X86rcp14s, SchedWriteFRcp.Scl,
+                               f32x_info>, EVEX_CD8<32, CD8VT1>,
+                               T8PD;
+defm VRCP14SDZ : avx512_fp14_s<0x4D, "vrcp14sd", X86rcp14s, SchedWriteFRcp.Scl,
+                               f64x_info>, VEX_W, EVEX_CD8<64, CD8VT1>,
+                               T8PD;
+defm VRSQRT14SSZ : avx512_fp14_s<0x4F, "vrsqrt14ss", X86rsqrt14s,
+                                 SchedWriteFRsqrt.Scl, f32x_info>,
+                                 EVEX_CD8<32, CD8VT1>, T8PD;
+defm VRSQRT14SDZ : avx512_fp14_s<0x4F, "vrsqrt14sd", X86rsqrt14s,
+                                 SchedWriteFRsqrt.Scl, f64x_info>, VEX_W,
+                                 EVEX_CD8<64, CD8VT1>, T8PD;
 
 /// avx512_fp14_p rcp14ps, rcp14pd, rsqrt14ps, rsqrt14pd
 multiclass avx512_fp14_p<bits<8> opc, string OpcodeStr, SDNode OpNode,
@@ -8383,10 +8383,10 @@ multiclass avx512_fp28_s<bits<8> opc, string OpcodeStr,X86VectorVTInfo _,
 
 multiclass avx512_eri_s<bits<8> opc, string OpcodeStr, SDNode OpNode,
                         X86FoldableSchedWrite sched> {
-  defm SS : avx512_fp28_s<opc, OpcodeStr#"ss", f32x_info, OpNode, sched>,
-              EVEX_CD8<32, CD8VT1>;
-  defm SD : avx512_fp28_s<opc, OpcodeStr#"sd", f64x_info, OpNode, sched>,
-              EVEX_CD8<64, CD8VT1>, VEX_W;
+  defm SSZ : avx512_fp28_s<opc, OpcodeStr#"ss", f32x_info, OpNode, sched>,
+               EVEX_CD8<32, CD8VT1>;
+  defm SDZ : avx512_fp28_s<opc, OpcodeStr#"sd", f64x_info, OpNode, sched>,
+               EVEX_CD8<64, CD8VT1>, VEX_W;
 }
 
 let Predicates = [HasERI] in {
@@ -8436,12 +8436,12 @@ multiclass avx512_fp28_p_round<bits<8> opc, string OpcodeStr, X86VectorVTInfo _,
 
 multiclass  avx512_eri<bits<8> opc, string OpcodeStr, SDNode OpNode,
                        X86SchedWriteWidths sched> {
-   defm PS : avx512_fp28_p<opc, OpcodeStr#"ps", v16f32_info, OpNode, sched.ZMM>,
-             avx512_fp28_p_round<opc, OpcodeStr#"ps", v16f32_info, OpNode, sched.ZMM>,
-             T8PD, EVEX_V512, EVEX_CD8<32, CD8VF>;
-   defm PD : avx512_fp28_p<opc, OpcodeStr#"pd", v8f64_info, OpNode, sched.ZMM>,
-             avx512_fp28_p_round<opc, OpcodeStr#"pd", v8f64_info, OpNode, sched.ZMM>,
-             T8PD, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
+   defm PSZ : avx512_fp28_p<opc, OpcodeStr#"ps", v16f32_info, OpNode, sched.ZMM>,
+              avx512_fp28_p_round<opc, OpcodeStr#"ps", v16f32_info, OpNode, sched.ZMM>,
+              T8PD, EVEX_V512, EVEX_CD8<32, CD8VF>;
+   defm PDZ : avx512_fp28_p<opc, OpcodeStr#"pd", v8f64_info, OpNode, sched.ZMM>,
+              avx512_fp28_p_round<opc, OpcodeStr#"pd", v8f64_info, OpNode, sched.ZMM>,
+              T8PD, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
 }
 
 multiclass avx512_fp_unaryop_packed<bits<8> opc, string OpcodeStr,
@@ -8683,15 +8683,15 @@ multiclass avx512_rndscale_scalar<bits<8> opc, string OpcodeStr,
   }
 }
 
-defm VRNDSCALESS : avx512_rndscale_scalar<0x0A, "vrndscaless",
-                                          SchedWriteFRnd.Scl, f32x_info>,
-                                          AVX512AIi8Base, EVEX_4V,
-                                          EVEX_CD8<32, CD8VT1>;
+defm VRNDSCALESSZ : avx512_rndscale_scalar<0x0A, "vrndscaless",
+                                           SchedWriteFRnd.Scl, f32x_info>,
+                                           AVX512AIi8Base, EVEX_4V,
+                                           EVEX_CD8<32, CD8VT1>;
 
-defm VRNDSCALESD : avx512_rndscale_scalar<0x0B, "vrndscalesd",
-                                          SchedWriteFRnd.Scl, f64x_info>,
-                                          VEX_W, AVX512AIi8Base, EVEX_4V,
-                                          EVEX_CD8<64, CD8VT1>;
+defm VRNDSCALESDZ : avx512_rndscale_scalar<0x0B, "vrndscalesd",
+                                           SchedWriteFRnd.Scl, f64x_info>,
+                                           VEX_W, AVX512AIi8Base, EVEX_4V,
+                                           EVEX_CD8<64, CD8VT1>;
 
 multiclass avx512_masked_scalar<SDNode OpNode, string OpcPrefix, SDNode Move,
                                 dag Mask, X86VectorVTInfo _, PatLeaf ZeroFP,
@@ -11096,12 +11096,12 @@ multiclass avx512_fixupimm_packed_all<X86SchedWriteWidths sched,
   }
 }
 
-defm VFIXUPIMMSS : avx512_fixupimm_scalar<0x55, "vfixupimm", X86VFixupimmScalar,
-                                          SchedWriteFAdd.Scl, f32x_info, v4i32x_info>,
-                         AVX512AIi8Base, VEX_LIG, EVEX_4V, EVEX_CD8<32, CD8VT1>;
-defm VFIXUPIMMSD : avx512_fixupimm_scalar<0x55, "vfixupimm", X86VFixupimmScalar,
-                                          SchedWriteFAdd.Scl, f64x_info, v2i64x_info>,
-                         AVX512AIi8Base, VEX_LIG, EVEX_4V, EVEX_CD8<64, CD8VT1>, VEX_W;
+defm VFIXUPIMMSSZ : avx512_fixupimm_scalar<0x55, "vfixupimm", X86VFixupimmScalar,
+                                           SchedWriteFAdd.Scl, f32x_info, v4i32x_info>,
+                          AVX512AIi8Base, VEX_LIG, EVEX_4V, EVEX_CD8<32, CD8VT1>;
+defm VFIXUPIMMSDZ : avx512_fixupimm_scalar<0x55, "vfixupimm", X86VFixupimmScalar,
+                                           SchedWriteFAdd.Scl, f64x_info, v2i64x_info>,
+                          AVX512AIi8Base, VEX_LIG, EVEX_4V, EVEX_CD8<64, CD8VT1>, VEX_W;
 defm VFIXUPIMMPS : avx512_fixupimm_packed_all<SchedWriteFAdd, avx512vl_f32_info>,
                          EVEX_CD8<32, CD8VF>;
 defm VFIXUPIMMPD : avx512_fixupimm_packed_all<SchedWriteFAdd, avx512vl_f64_info>,
diff --git a/llvm/lib/Target/X86/X86InstrInfo.cpp b/llvm/lib/Target/X86/X86InstrInfo.cpp
index d92a99a6e67..2283de69f32 100644
--- a/llvm/lib/Target/X86/X86InstrInfo.cpp
+++ b/llvm/lib/Target/X86/X86InstrInfo.cpp
@@ -1010,12 +1010,12 @@ X86InstrInfo::X86InstrInfo(X86Subtarget &STI)
     { X86::VPSRLWZri,        X86::VPSRLWZmi,          0 },
     { X86::VRCP14PDZr,       X86::VRCP14PDZm,         0 },
     { X86::VRCP14PSZr,       X86::VRCP14PSZm,         0 },
-    { X86::VRCP28PDr,        X86::VRCP28PDm,          0 },
-    { X86::VRCP28PSr,        X86::VRCP28PSm,          0 },
+    { X86::VRCP28PDZr,       X86::VRCP28PDZm,         0 },
+    { X86::VRCP28PSZr,       X86::VRCP28PSZm,         0 },
     { X86::VRSQRT14PDZr,     X86::VRSQRT14PDZm,       0 },
     { X86::VRSQRT14PSZr,     X86::VRSQRT14PSZm,       0 },
-    { X86::VRSQRT28PDr,      X86::VRSQRT28PDm,        0 },
-    { X86::VRSQRT28PSr,      X86::VRSQRT28PSm,        0 },
+    { X86::VRSQRT28PDZr,     X86::VRSQRT28PDZm,       0 },
+    { X86::VRSQRT28PSZr,     X86::VRSQRT28PSZm,       0 },
     { X86::VSQRTPDZr,        X86::VSQRTPDZm,          0 },
     { X86::VSQRTPSZr,        X86::VSQRTPSZm,          0 },
     { X86::VUCOMISDZrr,      X86::VUCOMISDZrm,        0 },
@@ -2189,20 +2189,20 @@ X86InstrInfo::X86InstrInfo(X86Subtarget &STI)
     { X86::VRANGEPSZrri,      X86::VRANGEPSZrmi,        0 },
     { X86::VRANGESDZrri,      X86::VRANGESDZrmi,        TB_NO_REVERSE },
     { X86::VRANGESSZrri,      X86::VRANGESSZrmi,        TB_NO_REVERSE },
-    { X86::VRCP14SDrr,        X86::VRCP14SDrm,          TB_NO_REVERSE },
-    { X86::VRCP14SSrr,        X86::VRCP14SSrm,          TB_NO_REVERSE },
-    { X86::VRCP28SDr,         X86::VRCP28SDm,           TB_NO_REVERSE },
-    { X86::VRCP28SSr,         X86::VRCP28SSm,           TB_NO_REVERSE },
+    { X86::VRCP14SDZrr,       X86::VRCP14SDZrm,         TB_NO_REVERSE },
+    { X86::VRCP14SSZrr,       X86::VRCP14SSZrm,         TB_NO_REVERSE },
+    { X86::VRCP28SDZr,        X86::VRCP28SDZm,          TB_NO_REVERSE },
+    { X86::VRCP28SSZr,        X86::VRCP28SSZm,          TB_NO_REVERSE },
     { X86::VREDUCESDZrri,     X86::VREDUCESDZrmi,       TB_NO_REVERSE },
     { X86::VREDUCESSZrri,     X86::VREDUCESSZrmi,       TB_NO_REVERSE },
-    { X86::VRNDSCALESDr,      X86::VRNDSCALESDm,        0 },
-    { X86::VRNDSCALESDr_Int,  X86::VRNDSCALESDm_Int,    TB_NO_REVERSE },
-    { X86::VRNDSCALESSr,      X86::VRNDSCALESSm,        0 },
-    { X86::VRNDSCALESSr_Int,  X86::VRNDSCALESSm_Int,    TB_NO_REVERSE },
-    { X86::VRSQRT14SDrr,      X86::VRSQRT14SDrm,        TB_NO_REVERSE },
-    { X86::VRSQRT14SSrr,      X86::VRSQRT14SSrm,        TB_NO_REVERSE },
-    { X86::VRSQRT28SDr,       X86::VRSQRT28SDm,         TB_NO_REVERSE },
-    { X86::VRSQRT28SSr,       X86::VRSQRT28SSm,         TB_NO_REVERSE },
+    { X86::VRNDSCALESDZr,     X86::VRNDSCALESDZm,       0 },
+    { X86::VRNDSCALESDZr_Int, X86::VRNDSCALESDZm_Int,   TB_NO_REVERSE },
+    { X86::VRNDSCALESSZr,     X86::VRNDSCALESSZm,       0 },
+    { X86::VRNDSCALESSZr_Int, X86::VRNDSCALESSZm_Int,   TB_NO_REVERSE },
+    { X86::VRSQRT14SDZrr,     X86::VRSQRT14SDZrm,       TB_NO_REVERSE },
+    { X86::VRSQRT14SSZrr,     X86::VRSQRT14SSZrm,       TB_NO_REVERSE },
+    { X86::VRSQRT28SDZr,      X86::VRSQRT28SDZm,        TB_NO_REVERSE },
+    { X86::VRSQRT28SSZr,      X86::VRSQRT28SSZm,        TB_NO_REVERSE },
     { X86::VSCALEFPDZrr,      X86::VSCALEFPDZrm,        0 },
     { X86::VSCALEFPSZrr,      X86::VSCALEFPSZrm,        0 },
     { X86::VSCALEFSDZrr,      X86::VSCALEFSDZrm,        TB_NO_REVERSE },
@@ -2817,8 +2817,8 @@ X86InstrInfo::X86InstrInfo(X86Subtarget &STI)
     // AVX-512 instructions with 3 source operands.
     { X86::VFIXUPIMMPDZrri,       X86::VFIXUPIMMPDZrmi,       0 },
     { X86::VFIXUPIMMPSZrri,       X86::VFIXUPIMMPSZrmi,       0 },
-    { X86::VFIXUPIMMSDrri,        X86::VFIXUPIMMSDrmi,        TB_NO_REVERSE },
-    { X86::VFIXUPIMMSSrri,        X86::VFIXUPIMMSSrmi,        TB_NO_REVERSE },
+    { X86::VFIXUPIMMSDZrri,       X86::VFIXUPIMMSDZrmi,       TB_NO_REVERSE },
+    { X86::VFIXUPIMMSSZrri,       X86::VFIXUPIMMSSZrmi,       TB_NO_REVERSE },
     { X86::VPDPBUSDSZr,           X86::VPDPBUSDSZm,           0 },
     { X86::VPDPBUSDZr,            X86::VPDPBUSDZm,            0 },
     { X86::VPDPWSSDSZr,           X86::VPDPWSSDSZm,           0 },
@@ -8444,20 +8444,20 @@ static bool hasUndefRegUpdate(unsigned Opcode) {
   case X86::VCVTSS2SDZrrb_Int:
   case X86::VCVTSS2SDZrm:
   case X86::VCVTSS2SDZrm_Int:
-  case X86::VRNDSCALESDr:
-  case X86::VRNDSCALESDr_Int:
-  case X86::VRNDSCALESDrb_Int:
-  case X86::VRNDSCALESDm:
-  case X86::VRNDSCALESDm_Int:
-  case X86::VRNDSCALESSr:
-  case X86::VRNDSCALESSr_Int:
-  case X86::VRNDSCALESSrb_Int:
-  case X86::VRNDSCALESSm:
-  case X86::VRNDSCALESSm_Int:
-  case X86::VRCP14SSrr:
-  case X86::VRCP14SSrm:
-  case X86::VRSQRT14SSrr:
-  case X86::VRSQRT14SSrm:
+  case X86::VRNDSCALESDZr:
+  case X86::VRNDSCALESDZr_Int:
+  case X86::VRNDSCALESDZrb_Int:
+  case X86::VRNDSCALESDZm:
+  case X86::VRNDSCALESDZm_Int:
+  case X86::VRNDSCALESSZr:
+  case X86::VRNDSCALESSZr_Int:
+  case X86::VRNDSCALESSZrb_Int:
+  case X86::VRNDSCALESSZm:
+  case X86::VRNDSCALESSZm_Int:
+  case X86::VRCP14SSZrr:
+  case X86::VRCP14SSZrm:
+  case X86::VRSQRT14SSZrr:
+  case X86::VRSQRT14SSZrm:
   case X86::VSQRTSSZr:
   case X86::VSQRTSSZr_Int:
   case X86::VSQRTSSZrb_Int: