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| author | Nirav Dave <niravd@google.com> | 2017-02-02 18:24:55 +0000 |
|---|---|---|
| committer | Nirav Dave <niravd@google.com> | 2017-02-02 18:24:55 +0000 |
| commit | 93f9d5ce0465d40b77af11b63adc8eb61429dddb (patch) | |
| tree | af72812886770674bf148c7b2d74d9ba44eb3094 /llvm/lib/Target | |
| parent | 827600deaf7b35ca55bcee4e2b226bb669aaf299 (diff) | |
| download | bcm5719-llvm-93f9d5ce0465d40b77af11b63adc8eb61429dddb.tar.gz bcm5719-llvm-93f9d5ce0465d40b77af11b63adc8eb61429dddb.zip | |
Revert "In visitSTORE, always use FindBetterChain, rather than only when UseAA is enabled."
This reverts commit r293893 which is miscompiling lua on ARM and
bootstrapping for x86-windows.
llvm-svn: 293915
Diffstat (limited to 'llvm/lib/Target')
| -rw-r--r-- | llvm/lib/Target/AArch64/AArch64ISelLowering.cpp | 2 | ||||
| -rw-r--r-- | llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp | 10 | ||||
| -rw-r--r-- | llvm/lib/Target/ARM/ARMISelLowering.h | 5 |
3 files changed, 11 insertions, 6 deletions
diff --git a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp index 5929daa2629..8fb9c5c4a38 100644 --- a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp +++ b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp @@ -9254,7 +9254,7 @@ static SDValue performSTORECombine(SDNode *N, return SDValue(); } -/// This function handles the log2-shuffle pattern produced by the + /// This function handles the log2-shuffle pattern produced by the /// LoopVectorizer for the across vector reduction. It consists of /// log2(NumVectorElements) steps and, in each step, 2^(s) elements /// are reduced, where s is an induction variable from 0 to diff --git a/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp b/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp index d48eac4b0fe..3350654daad 100644 --- a/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp +++ b/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp @@ -451,6 +451,16 @@ AMDGPUTargetLowering::AMDGPUTargetLowering(const TargetMachine &TM, PredictableSelectIsExpensive = false; + // We want to find all load dependencies for long chains of stores to enable + // merging into very wide vectors. The problem is with vectors with > 4 + // elements. MergeConsecutiveStores will attempt to merge these because x8/x16 + // vectors are a legal type, even though we have to split the loads + // usually. When we can more precisely specify load legality per address + // space, we should be able to make FindBetterChain/MergeConsecutiveStores + // smarter so that they can figure out what to do in 2 iterations without all + // N > 4 stores on the same chain. + GatherAllAliasesMaxDepth = 16; + // FIXME: Need to really handle these. MaxStoresPerMemcpy = 4096; MaxStoresPerMemmove = 4096; diff --git a/llvm/lib/Target/ARM/ARMISelLowering.h b/llvm/lib/Target/ARM/ARMISelLowering.h index 2b4cdf92ea9..84c6eb845bb 100644 --- a/llvm/lib/Target/ARM/ARMISelLowering.h +++ b/llvm/lib/Target/ARM/ARMISelLowering.h @@ -500,11 +500,6 @@ class InstrItineraryData; bool canCombineStoreAndExtract(Type *VectorTy, Value *Idx, unsigned &Cost) const override; - bool canMergeStoresTo(EVT MemVT) const override { - // Do not merge to larger than i32. - return (MemVT.getSizeInBits() <= 32); - } - bool isCheapToSpeculateCttz() const override; bool isCheapToSpeculateCtlz() const override; |

