diff options
| author | Craig Topper <craig.topper@intel.com> | 2019-05-19 01:01:46 +0000 |
|---|---|---|
| committer | Craig Topper <craig.topper@intel.com> | 2019-05-19 01:01:46 +0000 |
| commit | 3164b50af7a43072d23da4345d594dd5bf9b8ca7 (patch) | |
| tree | 40f6e37d7efe0ebc5e8ae90d1defaeb6b209a2ce /llvm/lib/Target | |
| parent | 4b105f53082bba3a34d4b4585cdd4da13fc0be81 (diff) | |
| download | bcm5719-llvm-3164b50af7a43072d23da4345d594dd5bf9b8ca7.tar.gz bcm5719-llvm-3164b50af7a43072d23da4345d594dd5bf9b8ca7.zip | |
[X86] Remove combineShift function. Just dispatch directly to the handler for each flavor from the main switch. NFC
llvm-svn: 361108
Diffstat (limited to 'llvm/lib/Target')
| -rw-r--r-- | llvm/lib/Target/X86/X86ISelLowering.cpp | 24 |
1 files changed, 3 insertions, 21 deletions
diff --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp index 4787741cb9b..7a3982e9008 100644 --- a/llvm/lib/Target/X86/X86ISelLowering.cpp +++ b/llvm/lib/Target/X86/X86ISelLowering.cpp @@ -37083,24 +37083,6 @@ static SDValue combineShiftRightLogical(SDNode *N, SelectionDAG &DAG, return SDValue(); } -static SDValue combineShift(SDNode* N, SelectionDAG &DAG, - TargetLowering::DAGCombinerInfo &DCI, - const X86Subtarget &Subtarget) { - if (N->getOpcode() == ISD::SHL) - if (SDValue V = combineShiftLeft(N, DAG)) - return V; - - if (N->getOpcode() == ISD::SRA) - if (SDValue V = combineShiftRightArithmetic(N, DAG)) - return V; - - if (N->getOpcode() == ISD::SRL) - if (SDValue V = combineShiftRightLogical(N, DAG, DCI)) - return V; - - return SDValue(); -} - static SDValue combineVectorPack(SDNode *N, SelectionDAG &DAG, TargetLowering::DAGCombinerInfo &DCI, const X86Subtarget &Subtarget) { @@ -43258,9 +43240,9 @@ SDValue X86TargetLowering::PerformDAGCombine(SDNode *N, case X86ISD::SBB: return combineSBB(N, DAG); case X86ISD::ADC: return combineADC(N, DAG, DCI); case ISD::MUL: return combineMul(N, DAG, DCI, Subtarget); - case ISD::SHL: - case ISD::SRA: - case ISD::SRL: return combineShift(N, DAG, DCI, Subtarget); + case ISD::SHL: return combineShiftLeft(N, DAG); + case ISD::SRA: return combineShiftRightArithmetic(N, DAG); + case ISD::SRL: return combineShiftRightLogical(N, DAG, DCI); case ISD::AND: return combineAnd(N, DAG, DCI, Subtarget); case ISD::OR: return combineOr(N, DAG, DCI, Subtarget); case ISD::XOR: return combineXor(N, DAG, DCI, Subtarget); |

