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| author | Stanislav Mekhanoshin <Stanislav.Mekhanoshin@amd.com> | 2018-10-03 00:00:41 +0000 |
|---|---|---|
| committer | Stanislav Mekhanoshin <Stanislav.Mekhanoshin@amd.com> | 2018-10-03 00:00:41 +0000 |
| commit | 1821513e2f9c02af81856977f3a0356c89f2b32b (patch) | |
| tree | 83fcbc6de7880b2cec5c13b1c91a1ccee0566477 /llvm/lib/Target | |
| parent | b02ba99e91ed89124401d2b9113a1cfa54fa76d9 (diff) | |
| download | bcm5719-llvm-1821513e2f9c02af81856977f3a0356c89f2b32b.tar.gz bcm5719-llvm-1821513e2f9c02af81856977f3a0356c89f2b32b.zip | |
[AMDGPU] Assert in getOpSize() there are no sub-dword subregs
Differential Revision: https://reviews.llvm.org/D52769
llvm-svn: 343648
Diffstat (limited to 'llvm/lib/Target')
| -rw-r--r-- | llvm/lib/Target/AMDGPU/SIInstrInfo.h | 7 |
1 files changed, 6 insertions, 1 deletions
diff --git a/llvm/lib/Target/AMDGPU/SIInstrInfo.h b/llvm/lib/Target/AMDGPU/SIInstrInfo.h index 4214046143c..478e16e2be7 100644 --- a/llvm/lib/Target/AMDGPU/SIInstrInfo.h +++ b/llvm/lib/Target/AMDGPU/SIInstrInfo.h @@ -732,8 +732,13 @@ public: unsigned getOpSize(const MachineInstr &MI, unsigned OpNo) const { const MachineOperand &MO = MI.getOperand(OpNo); if (MO.isReg()) { - if (unsigned SubReg = MO.getSubReg()) + if (unsigned SubReg = MO.getSubReg()) { + assert(RI.getRegSizeInBits(*RI.getSubClassWithSubReg( + MI.getParent()->getParent()->getRegInfo(). + getRegClass(MO.getReg()), SubReg)) >= 32 && + "Sub-dword subregs are not supported"); return RI.getSubRegIndexLaneMask(SubReg).getNumLanes() * 4; + } } return RI.getRegSizeInBits(*getOpRegClass(MI, OpNo)) / 8; } |
